sram.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * OMAP SRAM detection and management
  5. *
  6. * Copyright (C) 2005 Nokia Corporation
  7. * Written by Tony Lindgren <[email protected]>
  8. *
  9. * Copyright (C) 2009-2012 Texas Instruments
  10. * Added OMAP4/5 support - Santosh Shilimkar <[email protected]>
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/io.h>
  16. #include <asm/fncpy.h>
  17. #include <asm/tlb.h>
  18. #include <asm/cacheflush.h>
  19. #include <asm/set_memory.h>
  20. #include <asm/mach/map.h>
  21. #include "soc.h"
  22. #include "iomap.h"
  23. #include "prm2xxx_3xxx.h"
  24. #include "sdrc.h"
  25. #include "sram.h"
  26. #define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
  27. #define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
  28. #define SRAM_BOOTLOADER_SZ 0x00
  29. #define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
  30. #define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
  31. #define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
  32. #define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
  33. #define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
  34. #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
  35. #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
  36. #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
  37. #define GP_DEVICE 0x300
  38. #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
  39. static unsigned long omap_sram_start;
  40. static unsigned long omap_sram_size;
  41. static void __iomem *omap_sram_base;
  42. static unsigned long omap_sram_skip;
  43. static void __iomem *omap_sram_ceil;
  44. /*
  45. * Memory allocator for SRAM: calculates the new ceiling address
  46. * for pushing a function using the fncpy API.
  47. *
  48. * Note that fncpy requires the returned address to be aligned
  49. * to an 8-byte boundary.
  50. */
  51. static void *omap_sram_push_address(unsigned long size)
  52. {
  53. unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
  54. available = omap_sram_ceil - (omap_sram_base + omap_sram_skip);
  55. if (size > available) {
  56. pr_err("Not enough space in SRAM\n");
  57. return NULL;
  58. }
  59. new_ceil -= size;
  60. new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
  61. omap_sram_ceil = IOMEM(new_ceil);
  62. return (void __force *)omap_sram_ceil;
  63. }
  64. void *omap_sram_push(void *funcp, unsigned long size)
  65. {
  66. void *sram;
  67. unsigned long base;
  68. int pages;
  69. void *dst = NULL;
  70. sram = omap_sram_push_address(size);
  71. if (!sram)
  72. return NULL;
  73. base = (unsigned long)sram & PAGE_MASK;
  74. pages = PAGE_ALIGN(size) / PAGE_SIZE;
  75. set_memory_rw(base, pages);
  76. dst = fncpy(sram, funcp, size);
  77. set_memory_ro(base, pages);
  78. set_memory_x(base, pages);
  79. return dst;
  80. }
  81. /*
  82. * The SRAM context is lost during off-idle and stack
  83. * needs to be reset.
  84. */
  85. static void omap_sram_reset(void)
  86. {
  87. omap_sram_ceil = omap_sram_base + omap_sram_size;
  88. }
  89. /*
  90. * Depending on the target RAMFS firewall setup, the public usable amount of
  91. * SRAM varies. The default accessible size for all device types is 2k. A GP
  92. * device allows ARM11 but not other initiators for full size. This
  93. * functionality seems ok until some nice security API happens.
  94. */
  95. static int is_sram_locked(void)
  96. {
  97. if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
  98. /* RAMFW: R/W access to all initiators for all qualifier sets */
  99. if (cpu_is_omap242x()) {
  100. writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
  101. writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
  102. writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
  103. }
  104. if (cpu_is_omap34xx()) {
  105. writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
  106. writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
  107. writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
  108. writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
  109. writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
  110. }
  111. return 0;
  112. } else
  113. return 1; /* assume locked with no PPA or security driver */
  114. }
  115. /*
  116. * The amount of SRAM depends on the core type.
  117. * Note that we cannot try to test for SRAM here because writes
  118. * to secure SRAM will hang the system. Also the SRAM is not
  119. * yet mapped at this point.
  120. */
  121. static void __init omap_detect_sram(void)
  122. {
  123. omap_sram_skip = SRAM_BOOTLOADER_SZ;
  124. if (is_sram_locked()) {
  125. if (cpu_is_omap34xx()) {
  126. omap_sram_start = OMAP3_SRAM_PUB_PA;
  127. if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
  128. (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
  129. omap_sram_size = 0x7000; /* 28K */
  130. omap_sram_skip += SZ_16K;
  131. } else {
  132. omap_sram_size = 0x8000; /* 32K */
  133. }
  134. } else {
  135. omap_sram_start = OMAP2_SRAM_PUB_PA;
  136. omap_sram_size = 0x800; /* 2K */
  137. }
  138. } else {
  139. if (cpu_is_omap34xx()) {
  140. omap_sram_start = OMAP3_SRAM_PA;
  141. omap_sram_size = 0x10000; /* 64K */
  142. } else {
  143. omap_sram_start = OMAP2_SRAM_PA;
  144. if (cpu_is_omap242x())
  145. omap_sram_size = 0xa0000; /* 640K */
  146. else if (cpu_is_omap243x())
  147. omap_sram_size = 0x10000; /* 64K */
  148. }
  149. }
  150. }
  151. /*
  152. * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
  153. */
  154. static void __init omap2_map_sram(void)
  155. {
  156. unsigned long base;
  157. int pages;
  158. int cached = 1;
  159. if (cpu_is_omap34xx()) {
  160. /*
  161. * SRAM must be marked as non-cached on OMAP3 since the
  162. * CORE DPLL M2 divider change code (in SRAM) runs with the
  163. * SDRAM controller disabled, and if it is marked cached,
  164. * the ARM may attempt to write cache lines back to SDRAM
  165. * which will cause the system to hang.
  166. */
  167. cached = 0;
  168. }
  169. if (omap_sram_size == 0)
  170. return;
  171. omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
  172. omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size, cached);
  173. if (!omap_sram_base) {
  174. pr_err("SRAM: Could not map\n");
  175. return;
  176. }
  177. omap_sram_reset();
  178. /*
  179. * Looks like we need to preserve some bootloader code at the
  180. * beginning of SRAM for jumping to flash for reboot to work...
  181. */
  182. memset_io(omap_sram_base + omap_sram_skip, 0,
  183. omap_sram_size - omap_sram_skip);
  184. base = (unsigned long)omap_sram_base;
  185. pages = PAGE_ALIGN(omap_sram_size) / PAGE_SIZE;
  186. set_memory_ro(base, pages);
  187. set_memory_x(base, pages);
  188. }
  189. static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
  190. u32 base_cs, u32 force_unlock);
  191. void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
  192. u32 base_cs, u32 force_unlock)
  193. {
  194. BUG_ON(!_omap2_sram_ddr_init);
  195. _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
  196. base_cs, force_unlock);
  197. }
  198. static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
  199. u32 mem_type);
  200. void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
  201. {
  202. BUG_ON(!_omap2_sram_reprogram_sdrc);
  203. _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
  204. }
  205. static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
  206. u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
  207. {
  208. BUG_ON(!_omap2_set_prcm);
  209. return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
  210. }
  211. #ifdef CONFIG_SOC_OMAP2420
  212. static int __init omap242x_sram_init(void)
  213. {
  214. _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
  215. omap242x_sram_ddr_init_sz);
  216. _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
  217. omap242x_sram_reprogram_sdrc_sz);
  218. _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
  219. omap242x_sram_set_prcm_sz);
  220. return 0;
  221. }
  222. #else
  223. static inline int omap242x_sram_init(void)
  224. {
  225. return 0;
  226. }
  227. #endif
  228. #ifdef CONFIG_SOC_OMAP2430
  229. static int __init omap243x_sram_init(void)
  230. {
  231. _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
  232. omap243x_sram_ddr_init_sz);
  233. _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
  234. omap243x_sram_reprogram_sdrc_sz);
  235. _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
  236. omap243x_sram_set_prcm_sz);
  237. return 0;
  238. }
  239. #else
  240. static inline int omap243x_sram_init(void)
  241. {
  242. return 0;
  243. }
  244. #endif
  245. #ifdef CONFIG_ARCH_OMAP3
  246. void omap3_sram_restore_context(void)
  247. {
  248. omap_sram_reset();
  249. omap_push_sram_idle();
  250. }
  251. static inline int omap34xx_sram_init(void)
  252. {
  253. omap3_sram_restore_context();
  254. return 0;
  255. }
  256. #else
  257. static inline int omap34xx_sram_init(void)
  258. {
  259. return 0;
  260. }
  261. #endif /* CONFIG_ARCH_OMAP3 */
  262. int __init omap_sram_init(void)
  263. {
  264. omap_detect_sram();
  265. omap2_map_sram();
  266. if (cpu_is_omap242x())
  267. omap242x_sram_init();
  268. else if (cpu_is_omap2430())
  269. omap243x_sram_init();
  270. else if (cpu_is_omap34xx())
  271. omap34xx_sram_init();
  272. return 0;
  273. }