sdrc2xxx.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/mach-omap2/sdrc2xxx.c
  4. *
  5. * SDRAM timing related functions for OMAP2xxx
  6. *
  7. * Copyright (C) 2005, 2008 Texas Instruments Inc.
  8. * Copyright (C) 2005, 2008 Nokia Corporation
  9. *
  10. * Tony Lindgren <[email protected]>
  11. * Paul Walmsley
  12. * Richard Woodruff <[email protected]>
  13. */
  14. #include <linux/module.h>
  15. #include <linux/kernel.h>
  16. #include <linux/device.h>
  17. #include <linux/list.h>
  18. #include <linux/errno.h>
  19. #include <linux/delay.h>
  20. #include <linux/clk.h>
  21. #include <linux/io.h>
  22. #include "soc.h"
  23. #include "iomap.h"
  24. #include "common.h"
  25. #include "prm2xxx.h"
  26. #include "clock.h"
  27. #include "sdrc.h"
  28. #include "sram.h"
  29. /* Memory timing, DLL mode flags */
  30. #define M_DDR 1
  31. #define M_LOCK_CTRL (1 << 2)
  32. #define M_UNLOCK 0
  33. #define M_LOCK 1
  34. static struct memory_timings mem_timings;
  35. static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
  36. static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
  37. {
  38. return mem_timings.slow_dll_ctrl;
  39. }
  40. static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
  41. {
  42. return mem_timings.fast_dll_ctrl;
  43. }
  44. static u32 omap2xxx_sdrc_get_type(void)
  45. {
  46. return mem_timings.m_type;
  47. }
  48. /*
  49. * Check the DLL lock state, and return tue if running in unlock mode.
  50. * This is needed to compensate for the shifted DLL value in unlock mode.
  51. */
  52. u32 omap2xxx_sdrc_dll_is_unlocked(void)
  53. {
  54. /* dlla and dllb are a set */
  55. u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
  56. if ((dll_state & (1 << 2)) == (1 << 2))
  57. return 1;
  58. else
  59. return 0;
  60. }
  61. /*
  62. * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
  63. * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
  64. * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
  65. *
  66. * Used by the clock framework during CORE DPLL changes
  67. */
  68. u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
  69. {
  70. u32 dll_ctrl, m_type;
  71. u32 prev = curr_perf_level;
  72. unsigned long flags;
  73. if ((curr_perf_level == level) && !force)
  74. return prev;
  75. if (level == CORE_CLK_SRC_DPLL)
  76. dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
  77. else if (level == CORE_CLK_SRC_DPLL_X2)
  78. dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
  79. else
  80. return prev;
  81. m_type = omap2xxx_sdrc_get_type();
  82. local_irq_save(flags);
  83. /*
  84. * XXX These calls should be abstracted out through a
  85. * prm2xxx.c function
  86. */
  87. if (cpu_is_omap2420())
  88. writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP);
  89. else
  90. writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP);
  91. omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
  92. curr_perf_level = level;
  93. local_irq_restore(flags);
  94. return prev;
  95. }
  96. /* Used by the clock framework during CORE DPLL changes */
  97. void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
  98. {
  99. unsigned long dll_cnt;
  100. u32 fast_dll = 0;
  101. /* DDR = 1, SDR = 0 */
  102. mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
  103. /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
  104. * In the case of 2422, its ok to use CS1 instead of CS0.
  105. */
  106. if (cpu_is_omap2422())
  107. mem_timings.base_cs = 1;
  108. else
  109. mem_timings.base_cs = 0;
  110. if (mem_timings.m_type != M_DDR)
  111. return;
  112. /* With DDR we need to determine the low frequency DLL value */
  113. if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
  114. mem_timings.dll_mode = M_UNLOCK;
  115. else
  116. mem_timings.dll_mode = M_LOCK;
  117. if (mem_timings.base_cs == 0) {
  118. fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
  119. dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
  120. } else {
  121. fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
  122. dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
  123. }
  124. if (force_lock_to_unlock_mode) {
  125. fast_dll &= ~0xff00;
  126. fast_dll |= dll_cnt; /* Current lock mode */
  127. }
  128. /* set fast timings with DLL filter disabled */
  129. mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
  130. /* No disruptions, DDR will be offline & C-ABI not followed */
  131. omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
  132. mem_timings.fast_dll_ctrl,
  133. mem_timings.base_cs,
  134. force_lock_to_unlock_mode);
  135. mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
  136. /* Turn status into unlock ctrl */
  137. mem_timings.slow_dll_ctrl |=
  138. ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
  139. /* 90 degree phase for anything below 133MHz + disable DLL filter */
  140. mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
  141. }