sdrc.h 6.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. #ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H
  3. #define __ARCH_ARM_MACH_OMAP2_SDRC_H
  4. /*
  5. * OMAP2/3 SDRC/SMS macros and prototypes
  6. *
  7. * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc.
  8. * Copyright (C) 2007-2008 Nokia Corporation
  9. *
  10. * Paul Walmsley
  11. * Tony Lindgren
  12. * Richard Woodruff
  13. */
  14. #undef DEBUG
  15. #ifndef __ASSEMBLER__
  16. #include <linux/io.h>
  17. extern void __iomem *omap2_sdrc_base;
  18. extern void __iomem *omap2_sms_base;
  19. #define OMAP_SDRC_REGADDR(reg) (omap2_sdrc_base + (reg))
  20. #define OMAP_SMS_REGADDR(reg) (omap2_sms_base + (reg))
  21. /* SDRC global register get/set */
  22. static inline void sdrc_write_reg(u32 val, u16 reg)
  23. {
  24. writel_relaxed(val, OMAP_SDRC_REGADDR(reg));
  25. }
  26. static inline u32 sdrc_read_reg(u16 reg)
  27. {
  28. return readl_relaxed(OMAP_SDRC_REGADDR(reg));
  29. }
  30. /* SMS global register get/set */
  31. static inline void sms_write_reg(u32 val, u16 reg)
  32. {
  33. writel_relaxed(val, OMAP_SMS_REGADDR(reg));
  34. }
  35. static inline u32 sms_read_reg(u16 reg)
  36. {
  37. return readl_relaxed(OMAP_SMS_REGADDR(reg));
  38. }
  39. extern void omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms);
  40. /**
  41. * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
  42. * @rate: SDRC clock rate (in Hz)
  43. * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
  44. * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
  45. * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
  46. * @mr: Value to program to SDRC_MR for this rate
  47. *
  48. * This structure holds a pre-computed set of register values for the
  49. * SDRC for a given SDRC clock rate and SDRAM chip. These are
  50. * intended to be pre-computed and specified in an array in the board-*.c
  51. * files. The structure is keyed off the 'rate' field.
  52. */
  53. struct omap_sdrc_params {
  54. unsigned long rate;
  55. u32 actim_ctrla;
  56. u32 actim_ctrlb;
  57. u32 rfr_ctrl;
  58. u32 mr;
  59. };
  60. #ifdef CONFIG_SOC_HAS_OMAP2_SDRC
  61. void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
  62. struct omap_sdrc_params *sdrc_cs1);
  63. #else
  64. static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
  65. struct omap_sdrc_params *sdrc_cs1) {};
  66. #endif
  67. int omap2_sdrc_get_params(unsigned long r,
  68. struct omap_sdrc_params **sdrc_cs0,
  69. struct omap_sdrc_params **sdrc_cs1);
  70. void omap2_sms_save_context(void);
  71. void omap2_sms_restore_context(void);
  72. struct memory_timings {
  73. u32 m_type; /* ddr = 1, sdr = 0 */
  74. u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
  75. u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
  76. u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
  77. u32 base_cs; /* base chip select to use for calculations */
  78. };
  79. extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
  80. struct omap_sdrc_params *rx51_get_sdram_timings(void);
  81. u32 omap2xxx_sdrc_dll_is_unlocked(void);
  82. u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
  83. #else
  84. #define OMAP242X_SDRC_REGADDR(reg) \
  85. OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
  86. #define OMAP243X_SDRC_REGADDR(reg) \
  87. OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
  88. #define OMAP34XX_SDRC_REGADDR(reg) \
  89. OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
  90. #endif /* __ASSEMBLER__ */
  91. /* Minimum frequency that the SDRC DLL can lock at */
  92. #define MIN_SDRC_DLL_LOCK_FREQ 83000000
  93. /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
  94. #define SDRC_MPURATE_SCALE 8
  95. /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
  96. #define SDRC_MPURATE_BASE_SHIFT 9
  97. /*
  98. * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
  99. * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
  100. */
  101. #define SDRC_MPURATE_LOOPS 96
  102. /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
  103. #define SDRC_SYSCONFIG 0x010
  104. #define SDRC_CS_CFG 0x040
  105. #define SDRC_SHARING 0x044
  106. #define SDRC_ERR_TYPE 0x04C
  107. #define SDRC_DLLA_CTRL 0x060
  108. #define SDRC_DLLA_STATUS 0x064
  109. #define SDRC_DLLB_CTRL 0x068
  110. #define SDRC_DLLB_STATUS 0x06C
  111. #define SDRC_POWER 0x070
  112. #define SDRC_MCFG_0 0x080
  113. #define SDRC_MR_0 0x084
  114. #define SDRC_EMR2_0 0x08c
  115. #define SDRC_ACTIM_CTRL_A_0 0x09c
  116. #define SDRC_ACTIM_CTRL_B_0 0x0a0
  117. #define SDRC_RFR_CTRL_0 0x0a4
  118. #define SDRC_MANUAL_0 0x0a8
  119. #define SDRC_MCFG_1 0x0B0
  120. #define SDRC_MR_1 0x0B4
  121. #define SDRC_EMR2_1 0x0BC
  122. #define SDRC_ACTIM_CTRL_A_1 0x0C4
  123. #define SDRC_ACTIM_CTRL_B_1 0x0C8
  124. #define SDRC_RFR_CTRL_1 0x0D4
  125. #define SDRC_MANUAL_1 0x0D8
  126. #define SDRC_POWER_AUTOCOUNT_SHIFT 8
  127. #define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
  128. #define SDRC_POWER_CLKCTRL_SHIFT 4
  129. #define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
  130. #define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
  131. /*
  132. * These values represent the number of memory clock cycles between
  133. * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
  134. * rows per device, and include a subtraction of a 50 cycle window in the
  135. * event that the autorefresh command is delayed due to other SDRC activity.
  136. * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
  137. * counter reaches 0.
  138. *
  139. * These represent optimal values for common parts, it won't work for all.
  140. * As long as you scale down, most parameters are still work, they just
  141. * become sub-optimal. The RFR value goes in the opposite direction. If you
  142. * don't adjust it down as your clock period increases the refresh interval
  143. * will not be met. Setting all parameters for complete worst case may work,
  144. * but may cut memory performance by 2x. Due to errata the DLLs need to be
  145. * unlocked and their value needs run time calibration. A dynamic call is
  146. * need for that as no single right value exists across production samples.
  147. *
  148. * Only the FULL speed values are given. Current code is such that rate
  149. * changes must be made at DPLLoutx2. The actual value adjustment for low
  150. * frequency operation will be handled by omap_set_performance()
  151. *
  152. * By having the boot loader boot up in the fastest L4 speed available likely
  153. * will result in something which you can switch between.
  154. */
  155. #define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
  156. #define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
  157. #define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
  158. #define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
  159. #define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
  160. /*
  161. * SMS register access
  162. */
  163. #define OMAP242X_SMS_REGADDR(reg) \
  164. (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
  165. #define OMAP243X_SMS_REGADDR(reg) \
  166. (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
  167. #define OMAP343X_SMS_REGADDR(reg) \
  168. (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
  169. /* SMS register offsets - read/write with sms_{read,write}_reg() */
  170. #define SMS_SYSCONFIG 0x010
  171. /* REVISIT: fill in other SMS registers here */
  172. #endif