sdrc.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * SMS/SDRC (SDRAM controller) common code for OMAP2/3
  4. *
  5. * Copyright (C) 2005, 2008 Texas Instruments Inc.
  6. * Copyright (C) 2005, 2008 Nokia Corporation
  7. *
  8. * Tony Lindgren <[email protected]>
  9. * Paul Walmsley
  10. * Richard Woodruff <[email protected]>
  11. */
  12. #undef DEBUG
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/device.h>
  16. #include <linux/list.h>
  17. #include <linux/errno.h>
  18. #include <linux/delay.h>
  19. #include <linux/clk.h>
  20. #include <linux/io.h>
  21. #include "common.h"
  22. #include "clock.h"
  23. #include "sdrc.h"
  24. static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
  25. void __iomem *omap2_sdrc_base;
  26. void __iomem *omap2_sms_base;
  27. struct omap2_sms_regs {
  28. u32 sms_sysconfig;
  29. };
  30. static struct omap2_sms_regs sms_context;
  31. /* SDRC_POWER register bits */
  32. #define SDRC_POWER_EXTCLKDIS_SHIFT 3
  33. #define SDRC_POWER_PWDENA_SHIFT 2
  34. #define SDRC_POWER_PAGEPOLICY_SHIFT 0
  35. /**
  36. * omap2_sms_save_context - Save SMS registers
  37. *
  38. * Save SMS registers that need to be restored after off mode.
  39. */
  40. void omap2_sms_save_context(void)
  41. {
  42. sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
  43. }
  44. /**
  45. * omap2_sms_restore_context - Restore SMS registers
  46. *
  47. * Restore SMS registers that need to be Restored after off mode.
  48. */
  49. void omap2_sms_restore_context(void)
  50. {
  51. sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
  52. }
  53. /**
  54. * omap2_sdrc_get_params - return SDRC register values for a given clock rate
  55. * @r: SDRC clock rate (in Hz)
  56. * @sdrc_cs0: chip select 0 ram timings **
  57. * @sdrc_cs1: chip select 1 ram timings **
  58. *
  59. * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
  60. * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
  61. * structs,for a given SDRC clock rate 'r'.
  62. * These parameters control various timing delays in the SDRAM controller
  63. * that are expressed in terms of the number of SDRC clock cycles to
  64. * wait; hence the clock rate dependency.
  65. *
  66. * Supports 2 different timing parameters for both chip selects.
  67. *
  68. * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
  69. * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
  70. * as sdrc_init_params_cs_0.
  71. *
  72. * Fills in the struct omap_sdrc_params * for each chip select.
  73. * Returns 0 upon success or -1 upon failure.
  74. */
  75. int omap2_sdrc_get_params(unsigned long r,
  76. struct omap_sdrc_params **sdrc_cs0,
  77. struct omap_sdrc_params **sdrc_cs1)
  78. {
  79. struct omap_sdrc_params *sp0, *sp1;
  80. if (!sdrc_init_params_cs0)
  81. return -1;
  82. sp0 = sdrc_init_params_cs0;
  83. sp1 = sdrc_init_params_cs1;
  84. while (sp0->rate && sp0->rate != r) {
  85. sp0++;
  86. if (sdrc_init_params_cs1)
  87. sp1++;
  88. }
  89. if (!sp0->rate)
  90. return -1;
  91. *sdrc_cs0 = sp0;
  92. *sdrc_cs1 = sp1;
  93. return 0;
  94. }
  95. void __init omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms)
  96. {
  97. omap2_sdrc_base = sdrc;
  98. omap2_sms_base = sms;
  99. }
  100. /**
  101. * omap2_sdrc_init - initialize SMS, SDRC devices on boot
  102. * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
  103. * Support for 2 chip selects timings
  104. *
  105. * Turn on smart idle modes for SDRAM scheduler and controller.
  106. * Program a known-good configuration for the SDRC to deal with buggy
  107. * bootloaders.
  108. */
  109. void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
  110. struct omap_sdrc_params *sdrc_cs1)
  111. {
  112. u32 l;
  113. l = sms_read_reg(SMS_SYSCONFIG);
  114. l &= ~(0x3 << 3);
  115. l |= (0x2 << 3);
  116. sms_write_reg(l, SMS_SYSCONFIG);
  117. l = sdrc_read_reg(SDRC_SYSCONFIG);
  118. l &= ~(0x3 << 3);
  119. l |= (0x2 << 3);
  120. sdrc_write_reg(l, SDRC_SYSCONFIG);
  121. sdrc_init_params_cs0 = sdrc_cs0;
  122. sdrc_init_params_cs1 = sdrc_cs1;
  123. /* XXX Enable SRFRONIDLEREQ here also? */
  124. /*
  125. * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
  126. * can cause random memory corruption
  127. */
  128. l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
  129. (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
  130. sdrc_write_reg(l, SDRC_POWER);
  131. omap2_sms_save_context();
  132. }