opp2xxx.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
  4. *
  5. * Copyright (C) 2005-2009 Texas Instruments, Inc.
  6. * Copyright (C) 2004-2009 Nokia Corporation
  7. *
  8. * Richard Woodruff <[email protected]>
  9. *
  10. * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  11. * These configurations are characterized by voltage and speed for clocks.
  12. * The device is only validated for certain combinations. One way to express
  13. * these combinations is via the 'ratio's' which the clocks operate with
  14. * respect to each other. These ratio sets are for a given voltage/DPLL
  15. * setting. All configurations can be described by a DPLL setting and a ratio
  16. * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  17. *
  18. * 2430 differs from 2420 in that there are no more phase synchronizers used.
  19. * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  20. * 2430 (iva2.1, NOdsp, mdm)
  21. *
  22. * XXX Missing voltage data.
  23. *
  24. * THe format described in this file is deprecated. Once a reasonable
  25. * OPP API exists, the data in this file should be converted to use it.
  26. *
  27. * This is technically part of the OMAP2xxx clock code.
  28. */
  29. #ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
  30. #define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
  31. /**
  32. * struct prcm_config - define clock rates on a per-OPP basis (24xx)
  33. *
  34. * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  35. * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  36. * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  37. *
  38. * This is deprecated. As soon as we have a decent OPP API, we should
  39. * move all this stuff to it.
  40. */
  41. struct prcm_config {
  42. unsigned long xtal_speed; /* crystal rate */
  43. unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
  44. unsigned long mpu_speed; /* speed of MPU */
  45. unsigned long cm_clksel_mpu; /* mpu divider */
  46. unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
  47. unsigned long cm_clksel_gfx; /* gfx dividers */
  48. unsigned long cm_clksel1_core; /* major subsystem dividers */
  49. unsigned long cm_clksel1_pll; /* m,n */
  50. unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
  51. unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
  52. unsigned long base_sdrc_rfr; /* base refresh timing for a set */
  53. unsigned short flags;
  54. };
  55. /* Core fields for cm_clksel, not ratio governed */
  56. #define RX_CLKSEL_DSS1 (0x10 << 8)
  57. #define RX_CLKSEL_DSS2 (0x0 << 13)
  58. #define RX_CLKSEL_SSI (0x5 << 20)
  59. /*-------------------------------------------------------------------------
  60. * Voltage/DPLL ratios
  61. *-------------------------------------------------------------------------*/
  62. /* 2430 Ratio's, 2430-Ratio Config 1 */
  63. #define R1_CLKSEL_L3 (4 << 0)
  64. #define R1_CLKSEL_L4 (2 << 5)
  65. #define R1_CLKSEL_USB (4 << 25)
  66. #define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  67. RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  68. R1_CLKSEL_L4 | R1_CLKSEL_L3)
  69. #define R1_CLKSEL_MPU (2 << 0)
  70. #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
  71. #define R1_CLKSEL_DSP (2 << 0)
  72. #define R1_CLKSEL_DSP_IF (2 << 5)
  73. #define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF)
  74. #define R1_CLKSEL_GFX (2 << 0)
  75. #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
  76. #define R1_CLKSEL_MDM (4 << 0)
  77. #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
  78. /* 2430-Ratio Config 2 */
  79. #define R2_CLKSEL_L3 (6 << 0)
  80. #define R2_CLKSEL_L4 (2 << 5)
  81. #define R2_CLKSEL_USB (2 << 25)
  82. #define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI | \
  83. RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  84. R2_CLKSEL_L4 | R2_CLKSEL_L3)
  85. #define R2_CLKSEL_MPU (2 << 0)
  86. #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
  87. #define R2_CLKSEL_DSP (2 << 0)
  88. #define R2_CLKSEL_DSP_IF (3 << 5)
  89. #define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF)
  90. #define R2_CLKSEL_GFX (2 << 0)
  91. #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
  92. #define R2_CLKSEL_MDM (6 << 0)
  93. #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
  94. /* 2430-Ratio Bootm (BYPASS) */
  95. #define RB_CLKSEL_L3 (1 << 0)
  96. #define RB_CLKSEL_L4 (1 << 5)
  97. #define RB_CLKSEL_USB (1 << 25)
  98. #define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI | \
  99. RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  100. RB_CLKSEL_L4 | RB_CLKSEL_L3)
  101. #define RB_CLKSEL_MPU (1 << 0)
  102. #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
  103. #define RB_CLKSEL_DSP (1 << 0)
  104. #define RB_CLKSEL_DSP_IF (1 << 5)
  105. #define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF)
  106. #define RB_CLKSEL_GFX (1 << 0)
  107. #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
  108. #define RB_CLKSEL_MDM (1 << 0)
  109. #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
  110. /* 2420 Ratio Equivalents */
  111. #define RXX_CLKSEL_VLYNQ (0x12 << 15)
  112. #define RXX_CLKSEL_SSI (0x8 << 20)
  113. /* 2420-PRCM III 532MHz core */
  114. #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
  115. #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
  116. #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
  117. #define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
  118. RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
  119. RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
  120. RIII_CLKSEL_L3)
  121. #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
  122. #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
  123. #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
  124. #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
  125. #define RIII_SYNC_DSP (1 << 7) /* Enable sync */
  126. #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
  127. #define RIII_SYNC_IVA (1 << 13) /* Enable sync */
  128. #define RIII_CM_CLKSEL_DSP_VAL (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
  129. RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
  130. RIII_CLKSEL_DSP)
  131. #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
  132. #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
  133. /* 2420-PRCM II 600MHz core */
  134. #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
  135. #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
  136. #define RII_CLKSEL_USB (2 << 25) /* 50MHz */
  137. #define RII_CM_CLKSEL1_CORE_VAL (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \
  138. RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
  139. RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \
  140. RII_CLKSEL_L3)
  141. #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
  142. #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
  143. #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
  144. #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
  145. #define RII_SYNC_DSP (0 << 7) /* Bypass sync */
  146. #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
  147. #define RII_SYNC_IVA (0 << 13) /* Bypass sync */
  148. #define RII_CM_CLKSEL_DSP_VAL (RII_SYNC_IVA | RII_CLKSEL_IVA | \
  149. RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
  150. RII_CLKSEL_DSP)
  151. #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
  152. #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
  153. /* 2420-PRCM I 660MHz core */
  154. #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
  155. #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
  156. #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
  157. #define RI_CM_CLKSEL1_CORE_VAL (RI_CLKSEL_USB | \
  158. RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
  159. RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  160. RI_CLKSEL_L4 | RI_CLKSEL_L3)
  161. #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
  162. #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
  163. #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
  164. #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
  165. #define RI_SYNC_DSP (1 << 7) /* Activate sync */
  166. #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
  167. #define RI_SYNC_IVA (0 << 13) /* Bypass sync */
  168. #define RI_CM_CLKSEL_DSP_VAL (RI_SYNC_IVA | RI_CLKSEL_IVA | \
  169. RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
  170. RI_CLKSEL_DSP)
  171. #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
  172. #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
  173. /* 2420-PRCM VII (boot) */
  174. #define RVII_CLKSEL_L3 (1 << 0)
  175. #define RVII_CLKSEL_L4 (1 << 5)
  176. #define RVII_CLKSEL_DSS1 (1 << 8)
  177. #define RVII_CLKSEL_DSS2 (0 << 13)
  178. #define RVII_CLKSEL_VLYNQ (1 << 15)
  179. #define RVII_CLKSEL_SSI (1 << 20)
  180. #define RVII_CLKSEL_USB (1 << 25)
  181. #define RVII_CM_CLKSEL1_CORE_VAL (RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
  182. RVII_CLKSEL_VLYNQ | \
  183. RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \
  184. RVII_CLKSEL_L4 | RVII_CLKSEL_L3)
  185. #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
  186. #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
  187. #define RVII_CLKSEL_DSP (1 << 0)
  188. #define RVII_CLKSEL_DSP_IF (1 << 5)
  189. #define RVII_SYNC_DSP (0 << 7)
  190. #define RVII_CLKSEL_IVA (1 << 8)
  191. #define RVII_SYNC_IVA (0 << 13)
  192. #define RVII_CM_CLKSEL_DSP_VAL (RVII_SYNC_IVA | RVII_CLKSEL_IVA | \
  193. RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \
  194. RVII_CLKSEL_DSP)
  195. #define RVII_CLKSEL_GFX (1 << 0)
  196. #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
  197. /*-------------------------------------------------------------------------
  198. * 2430 Target modes: Along with each configuration the CPU has several
  199. * modes which goes along with them. Modes mainly are the addition of
  200. * describe DPLL combinations to go along with a ratio.
  201. *-------------------------------------------------------------------------*/
  202. /* Hardware governed */
  203. #define MX_48M_SRC (0 << 3)
  204. #define MX_54M_SRC (0 << 5)
  205. #define MX_APLLS_CLIKIN_12 (3 << 23)
  206. #define MX_APLLS_CLIKIN_13 (2 << 23)
  207. #define MX_APLLS_CLIKIN_19_2 (0 << 23)
  208. /*
  209. * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
  210. * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
  211. */
  212. #define M5A_DPLL_MULT_12 (133 << 12)
  213. #define M5A_DPLL_DIV_12 (5 << 8)
  214. #define M5A_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
  215. M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
  216. MX_APLLS_CLIKIN_12)
  217. #define M5A_DPLL_MULT_13 (61 << 12)
  218. #define M5A_DPLL_DIV_13 (2 << 8)
  219. #define M5A_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
  220. M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
  221. MX_APLLS_CLIKIN_13)
  222. #define M5A_DPLL_MULT_19 (55 << 12)
  223. #define M5A_DPLL_DIV_19 (3 << 8)
  224. #define M5A_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
  225. M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
  226. MX_APLLS_CLIKIN_19_2)
  227. /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
  228. #define M5B_DPLL_MULT_12 (50 << 12)
  229. #define M5B_DPLL_DIV_12 (2 << 8)
  230. #define M5B_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
  231. M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
  232. MX_APLLS_CLIKIN_12)
  233. #define M5B_DPLL_MULT_13 (200 << 12)
  234. #define M5B_DPLL_DIV_13 (12 << 8)
  235. #define M5B_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
  236. M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
  237. MX_APLLS_CLIKIN_13)
  238. #define M5B_DPLL_MULT_19 (125 << 12)
  239. #define M5B_DPLL_DIV_19 (31 << 8)
  240. #define M5B_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
  241. M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
  242. MX_APLLS_CLIKIN_19_2)
  243. /*
  244. * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
  245. */
  246. #define M4_DPLL_MULT_12 (133 << 12)
  247. #define M4_DPLL_DIV_12 (3 << 8)
  248. #define M4_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
  249. M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
  250. MX_APLLS_CLIKIN_12)
  251. #define M4_DPLL_MULT_13 (399 << 12)
  252. #define M4_DPLL_DIV_13 (12 << 8)
  253. #define M4_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
  254. M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
  255. MX_APLLS_CLIKIN_13)
  256. #define M4_DPLL_MULT_19 (145 << 12)
  257. #define M4_DPLL_DIV_19 (6 << 8)
  258. #define M4_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
  259. M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
  260. MX_APLLS_CLIKIN_19_2)
  261. /*
  262. * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
  263. */
  264. #define M3_DPLL_MULT_12 (55 << 12)
  265. #define M3_DPLL_DIV_12 (1 << 8)
  266. #define M3_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
  267. M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
  268. MX_APLLS_CLIKIN_12)
  269. #define M3_DPLL_MULT_13 (76 << 12)
  270. #define M3_DPLL_DIV_13 (2 << 8)
  271. #define M3_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
  272. M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
  273. MX_APLLS_CLIKIN_13)
  274. #define M3_DPLL_MULT_19 (17 << 12)
  275. #define M3_DPLL_DIV_19 (0 << 8)
  276. #define M3_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
  277. M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
  278. MX_APLLS_CLIKIN_19_2)
  279. /*
  280. * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
  281. */
  282. #define M2_DPLL_MULT_12 (55 << 12)
  283. #define M2_DPLL_DIV_12 (1 << 8)
  284. #define M2_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
  285. M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
  286. MX_APLLS_CLIKIN_12)
  287. /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
  288. * relock time issue */
  289. /* Core frequency changed from 330/165 to 329/164 MHz*/
  290. #define M2_DPLL_MULT_13 (76 << 12)
  291. #define M2_DPLL_DIV_13 (2 << 8)
  292. #define M2_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
  293. M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
  294. MX_APLLS_CLIKIN_13)
  295. #define M2_DPLL_MULT_19 (17 << 12)
  296. #define M2_DPLL_DIV_19 (0 << 8)
  297. #define M2_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
  298. M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
  299. MX_APLLS_CLIKIN_19_2)
  300. /* boot (boot) */
  301. #define MB_DPLL_MULT (1 << 12)
  302. #define MB_DPLL_DIV (0 << 8)
  303. #define MB_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
  304. MB_DPLL_DIV | MB_DPLL_MULT | \
  305. MX_APLLS_CLIKIN_12)
  306. #define MB_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
  307. MB_DPLL_DIV | MB_DPLL_MULT | \
  308. MX_APLLS_CLIKIN_13)
  309. #define MB_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
  310. MB_DPLL_DIV | MB_DPLL_MULT | \
  311. MX_APLLS_CLIKIN_19)
  312. /*
  313. * 2430 - chassis (sedna)
  314. * 165 (ratio1) same as above #2
  315. * 150 (ratio1)
  316. * 133 (ratio2) same as above #4
  317. * 110 (ratio2) same as above #3
  318. * 104 (ratio2)
  319. * boot (boot)
  320. */
  321. /* PRCM I target DPLL = 2*330MHz = 660MHz */
  322. #define MI_DPLL_MULT_12 (55 << 12)
  323. #define MI_DPLL_DIV_12 (1 << 8)
  324. #define MI_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
  325. MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
  326. MX_APLLS_CLIKIN_12)
  327. /*
  328. * 2420 Equivalent - mode registers
  329. * PRCM II , target DPLL = 2*300MHz = 600MHz
  330. */
  331. #define MII_DPLL_MULT_12 (50 << 12)
  332. #define MII_DPLL_DIV_12 (1 << 8)
  333. #define MII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
  334. MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
  335. MX_APLLS_CLIKIN_12)
  336. #define MII_DPLL_MULT_13 (300 << 12)
  337. #define MII_DPLL_DIV_13 (12 << 8)
  338. #define MII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
  339. MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
  340. MX_APLLS_CLIKIN_13)
  341. /* PRCM III target DPLL = 2*266 = 532MHz*/
  342. #define MIII_DPLL_MULT_12 (133 << 12)
  343. #define MIII_DPLL_DIV_12 (5 << 8)
  344. #define MIII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
  345. MIII_DPLL_DIV_12 | \
  346. MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12)
  347. #define MIII_DPLL_MULT_13 (266 << 12)
  348. #define MIII_DPLL_DIV_13 (12 << 8)
  349. #define MIII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
  350. MIII_DPLL_DIV_13 | \
  351. MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13)
  352. /* PRCM VII (boot bypass) */
  353. #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
  354. #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
  355. /* High and low operation value */
  356. #define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
  357. #define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
  358. /* MPU speed defines */
  359. #define S12M 12000000
  360. #define S13M 13000000
  361. #define S19M 19200000
  362. #define S26M 26000000
  363. #define S100M 100000000
  364. #define S133M 133000000
  365. #define S150M 150000000
  366. #define S164M 164000000
  367. #define S165M 165000000
  368. #define S199M 199000000
  369. #define S200M 200000000
  370. #define S266M 266000000
  371. #define S300M 300000000
  372. #define S329M 329000000
  373. #define S330M 330000000
  374. #define S399M 399000000
  375. #define S400M 400000000
  376. #define S532M 532000000
  377. #define S600M 600000000
  378. #define S658M 658000000
  379. #define S660M 660000000
  380. #define S798M 798000000
  381. extern const struct prcm_config omap2420_rate_table[];
  382. #ifdef CONFIG_SOC_OMAP2430
  383. extern const struct prcm_config omap2430_rate_table[];
  384. #else
  385. #define omap2430_rate_table NULL
  386. #endif
  387. extern const struct prcm_config *rate_table;
  388. extern const struct prcm_config *curr_prcm_set;
  389. #endif