io.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/mach-omap2/io.c
  4. *
  5. * OMAP2 I/O mapping code
  6. *
  7. * Copyright (C) 2005 Nokia Corporation
  8. * Copyright (C) 2007-2009 Texas Instruments
  9. *
  10. * Author:
  11. * Juha Yrjola <[email protected]>
  12. * Syed Khasim <[email protected]>
  13. *
  14. * Added OMAP4 support - Santosh Shilimkar <[email protected]>
  15. */
  16. #include <linux/module.h>
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/io.h>
  20. #include <linux/clk.h>
  21. #include <asm/tlb.h>
  22. #include <asm/mach/map.h>
  23. #include <linux/omap-dma.h>
  24. #include "omap_hwmod.h"
  25. #include "soc.h"
  26. #include "iomap.h"
  27. #include "voltage.h"
  28. #include "powerdomain.h"
  29. #include "clockdomain.h"
  30. #include "common.h"
  31. #include "clock.h"
  32. #include "clock2xxx.h"
  33. #include "clock3xxx.h"
  34. #include "sdrc.h"
  35. #include "control.h"
  36. #include "serial.h"
  37. #include "sram.h"
  38. #include "cm2xxx.h"
  39. #include "cm3xxx.h"
  40. #include "cm33xx.h"
  41. #include "cm44xx.h"
  42. #include "prm.h"
  43. #include "cm.h"
  44. #include "prcm_mpu44xx.h"
  45. #include "prminst44xx.h"
  46. #include "prm2xxx.h"
  47. #include "prm3xxx.h"
  48. #include "prm33xx.h"
  49. #include "prm44xx.h"
  50. #include "opp2xxx.h"
  51. #include "omap-secure.h"
  52. /*
  53. * omap_clk_soc_init: points to a function that does the SoC-specific
  54. * clock initializations
  55. */
  56. static int (*omap_clk_soc_init)(void);
  57. /*
  58. * The machine specific code may provide the extra mapping besides the
  59. * default mapping provided here.
  60. */
  61. #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
  62. static struct map_desc omap24xx_io_desc[] __initdata = {
  63. {
  64. .virtual = L3_24XX_VIRT,
  65. .pfn = __phys_to_pfn(L3_24XX_PHYS),
  66. .length = L3_24XX_SIZE,
  67. .type = MT_DEVICE
  68. },
  69. {
  70. .virtual = L4_24XX_VIRT,
  71. .pfn = __phys_to_pfn(L4_24XX_PHYS),
  72. .length = L4_24XX_SIZE,
  73. .type = MT_DEVICE
  74. },
  75. };
  76. #ifdef CONFIG_SOC_OMAP2420
  77. static struct map_desc omap242x_io_desc[] __initdata = {
  78. {
  79. .virtual = DSP_MEM_2420_VIRT,
  80. .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
  81. .length = DSP_MEM_2420_SIZE,
  82. .type = MT_DEVICE
  83. },
  84. {
  85. .virtual = DSP_IPI_2420_VIRT,
  86. .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
  87. .length = DSP_IPI_2420_SIZE,
  88. .type = MT_DEVICE
  89. },
  90. {
  91. .virtual = DSP_MMU_2420_VIRT,
  92. .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
  93. .length = DSP_MMU_2420_SIZE,
  94. .type = MT_DEVICE
  95. },
  96. };
  97. #endif
  98. #ifdef CONFIG_SOC_OMAP2430
  99. static struct map_desc omap243x_io_desc[] __initdata = {
  100. {
  101. .virtual = L4_WK_243X_VIRT,
  102. .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
  103. .length = L4_WK_243X_SIZE,
  104. .type = MT_DEVICE
  105. },
  106. {
  107. .virtual = OMAP243X_GPMC_VIRT,
  108. .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
  109. .length = OMAP243X_GPMC_SIZE,
  110. .type = MT_DEVICE
  111. },
  112. {
  113. .virtual = OMAP243X_SDRC_VIRT,
  114. .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
  115. .length = OMAP243X_SDRC_SIZE,
  116. .type = MT_DEVICE
  117. },
  118. {
  119. .virtual = OMAP243X_SMS_VIRT,
  120. .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
  121. .length = OMAP243X_SMS_SIZE,
  122. .type = MT_DEVICE
  123. },
  124. };
  125. #endif
  126. #endif
  127. #ifdef CONFIG_ARCH_OMAP3
  128. static struct map_desc omap34xx_io_desc[] __initdata = {
  129. {
  130. .virtual = L3_34XX_VIRT,
  131. .pfn = __phys_to_pfn(L3_34XX_PHYS),
  132. .length = L3_34XX_SIZE,
  133. .type = MT_DEVICE
  134. },
  135. {
  136. .virtual = L4_34XX_VIRT,
  137. .pfn = __phys_to_pfn(L4_34XX_PHYS),
  138. .length = L4_34XX_SIZE,
  139. .type = MT_DEVICE
  140. },
  141. {
  142. .virtual = OMAP34XX_GPMC_VIRT,
  143. .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
  144. .length = OMAP34XX_GPMC_SIZE,
  145. .type = MT_DEVICE
  146. },
  147. {
  148. .virtual = OMAP343X_SMS_VIRT,
  149. .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
  150. .length = OMAP343X_SMS_SIZE,
  151. .type = MT_DEVICE
  152. },
  153. {
  154. .virtual = OMAP343X_SDRC_VIRT,
  155. .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
  156. .length = OMAP343X_SDRC_SIZE,
  157. .type = MT_DEVICE
  158. },
  159. {
  160. .virtual = L4_PER_34XX_VIRT,
  161. .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
  162. .length = L4_PER_34XX_SIZE,
  163. .type = MT_DEVICE
  164. },
  165. {
  166. .virtual = L4_EMU_34XX_VIRT,
  167. .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
  168. .length = L4_EMU_34XX_SIZE,
  169. .type = MT_DEVICE
  170. },
  171. };
  172. #endif
  173. #ifdef CONFIG_SOC_TI81XX
  174. static struct map_desc omapti81xx_io_desc[] __initdata = {
  175. {
  176. .virtual = L4_34XX_VIRT,
  177. .pfn = __phys_to_pfn(L4_34XX_PHYS),
  178. .length = L4_34XX_SIZE,
  179. .type = MT_DEVICE
  180. }
  181. };
  182. #endif
  183. #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
  184. static struct map_desc omapam33xx_io_desc[] __initdata = {
  185. {
  186. .virtual = L4_34XX_VIRT,
  187. .pfn = __phys_to_pfn(L4_34XX_PHYS),
  188. .length = L4_34XX_SIZE,
  189. .type = MT_DEVICE
  190. },
  191. {
  192. .virtual = L4_WK_AM33XX_VIRT,
  193. .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
  194. .length = L4_WK_AM33XX_SIZE,
  195. .type = MT_DEVICE
  196. }
  197. };
  198. #endif
  199. #ifdef CONFIG_ARCH_OMAP4
  200. static struct map_desc omap44xx_io_desc[] __initdata = {
  201. {
  202. .virtual = L3_44XX_VIRT,
  203. .pfn = __phys_to_pfn(L3_44XX_PHYS),
  204. .length = L3_44XX_SIZE,
  205. .type = MT_DEVICE,
  206. },
  207. {
  208. .virtual = L4_44XX_VIRT,
  209. .pfn = __phys_to_pfn(L4_44XX_PHYS),
  210. .length = L4_44XX_SIZE,
  211. .type = MT_DEVICE,
  212. },
  213. {
  214. .virtual = L4_PER_44XX_VIRT,
  215. .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
  216. .length = L4_PER_44XX_SIZE,
  217. .type = MT_DEVICE,
  218. },
  219. };
  220. #endif
  221. #ifdef CONFIG_SOC_OMAP5
  222. static struct map_desc omap54xx_io_desc[] __initdata = {
  223. {
  224. .virtual = L3_54XX_VIRT,
  225. .pfn = __phys_to_pfn(L3_54XX_PHYS),
  226. .length = L3_54XX_SIZE,
  227. .type = MT_DEVICE,
  228. },
  229. {
  230. .virtual = L4_54XX_VIRT,
  231. .pfn = __phys_to_pfn(L4_54XX_PHYS),
  232. .length = L4_54XX_SIZE,
  233. .type = MT_DEVICE,
  234. },
  235. {
  236. .virtual = L4_WK_54XX_VIRT,
  237. .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
  238. .length = L4_WK_54XX_SIZE,
  239. .type = MT_DEVICE,
  240. },
  241. {
  242. .virtual = L4_PER_54XX_VIRT,
  243. .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
  244. .length = L4_PER_54XX_SIZE,
  245. .type = MT_DEVICE,
  246. },
  247. };
  248. #endif
  249. #ifdef CONFIG_SOC_DRA7XX
  250. static struct map_desc dra7xx_io_desc[] __initdata = {
  251. {
  252. .virtual = L4_CFG_MPU_DRA7XX_VIRT,
  253. .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
  254. .length = L4_CFG_MPU_DRA7XX_SIZE,
  255. .type = MT_DEVICE,
  256. },
  257. {
  258. .virtual = L3_MAIN_SN_DRA7XX_VIRT,
  259. .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
  260. .length = L3_MAIN_SN_DRA7XX_SIZE,
  261. .type = MT_DEVICE,
  262. },
  263. {
  264. .virtual = L4_PER1_DRA7XX_VIRT,
  265. .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
  266. .length = L4_PER1_DRA7XX_SIZE,
  267. .type = MT_DEVICE,
  268. },
  269. {
  270. .virtual = L4_PER2_DRA7XX_VIRT,
  271. .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
  272. .length = L4_PER2_DRA7XX_SIZE,
  273. .type = MT_DEVICE,
  274. },
  275. {
  276. .virtual = L4_PER3_DRA7XX_VIRT,
  277. .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
  278. .length = L4_PER3_DRA7XX_SIZE,
  279. .type = MT_DEVICE,
  280. },
  281. {
  282. .virtual = L4_CFG_DRA7XX_VIRT,
  283. .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
  284. .length = L4_CFG_DRA7XX_SIZE,
  285. .type = MT_DEVICE,
  286. },
  287. {
  288. .virtual = L4_WKUP_DRA7XX_VIRT,
  289. .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
  290. .length = L4_WKUP_DRA7XX_SIZE,
  291. .type = MT_DEVICE,
  292. },
  293. };
  294. #endif
  295. #ifdef CONFIG_SOC_OMAP2420
  296. void __init omap242x_map_io(void)
  297. {
  298. iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
  299. iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
  300. }
  301. #endif
  302. #ifdef CONFIG_SOC_OMAP2430
  303. void __init omap243x_map_io(void)
  304. {
  305. iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
  306. iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
  307. }
  308. #endif
  309. #ifdef CONFIG_ARCH_OMAP3
  310. void __init omap3_map_io(void)
  311. {
  312. iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
  313. }
  314. #endif
  315. #ifdef CONFIG_SOC_TI81XX
  316. void __init ti81xx_map_io(void)
  317. {
  318. iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
  319. }
  320. #endif
  321. #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
  322. void __init am33xx_map_io(void)
  323. {
  324. iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
  325. }
  326. #endif
  327. #ifdef CONFIG_ARCH_OMAP4
  328. void __init omap4_map_io(void)
  329. {
  330. iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
  331. omap_barriers_init();
  332. }
  333. #endif
  334. #ifdef CONFIG_SOC_OMAP5
  335. void __init omap5_map_io(void)
  336. {
  337. iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
  338. omap_barriers_init();
  339. }
  340. #endif
  341. #ifdef CONFIG_SOC_DRA7XX
  342. void __init dra7xx_map_io(void)
  343. {
  344. iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
  345. omap_barriers_init();
  346. }
  347. #endif
  348. /*
  349. * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
  350. *
  351. * Sets the CORE DPLL3 M2 divider to the same value that it's at
  352. * currently. This has the effect of setting the SDRC SDRAM AC timing
  353. * registers to the values currently defined by the kernel. Currently
  354. * only defined for OMAP3; will return 0 if called on OMAP2. Returns
  355. * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
  356. * or passes along the return value of clk_set_rate().
  357. */
  358. static int __init _omap2_init_reprogram_sdrc(void)
  359. {
  360. struct clk *dpll3_m2_ck;
  361. int v = -EINVAL;
  362. long rate;
  363. if (!cpu_is_omap34xx())
  364. return 0;
  365. dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
  366. if (IS_ERR(dpll3_m2_ck))
  367. return -EINVAL;
  368. rate = clk_get_rate(dpll3_m2_ck);
  369. pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
  370. v = clk_set_rate(dpll3_m2_ck, rate);
  371. if (v)
  372. pr_err("dpll3_m2_clk rate change failed: %d\n", v);
  373. clk_put(dpll3_m2_ck);
  374. return v;
  375. }
  376. #ifdef CONFIG_OMAP_HWMOD
  377. static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
  378. {
  379. return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
  380. }
  381. static void __init __maybe_unused omap_hwmod_init_postsetup(void)
  382. {
  383. u8 postsetup_state = _HWMOD_STATE_DEFAULT;
  384. /* Set the default postsetup state for all hwmods */
  385. omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
  386. }
  387. #else
  388. static inline void omap_hwmod_init_postsetup(void)
  389. {
  390. }
  391. #endif
  392. #ifdef CONFIG_SOC_OMAP2420
  393. void __init omap2420_init_early(void)
  394. {
  395. omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
  396. omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
  397. OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
  398. omap2_control_base_init();
  399. omap2xxx_check_revision();
  400. omap2_prcm_base_init();
  401. omap2xxx_voltagedomains_init();
  402. omap242x_powerdomains_init();
  403. omap242x_clockdomains_init();
  404. omap2420_hwmod_init();
  405. omap_hwmod_init_postsetup();
  406. omap_clk_soc_init = omap2420_dt_clk_init;
  407. rate_table = omap2420_rate_table;
  408. }
  409. void __init omap2420_init_late(void)
  410. {
  411. omap_pm_soc_init = omap2_pm_init;
  412. }
  413. #endif
  414. #ifdef CONFIG_SOC_OMAP2430
  415. void __init omap2430_init_early(void)
  416. {
  417. omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
  418. omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
  419. OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
  420. omap2_control_base_init();
  421. omap2xxx_check_revision();
  422. omap2_prcm_base_init();
  423. omap2xxx_voltagedomains_init();
  424. omap243x_powerdomains_init();
  425. omap243x_clockdomains_init();
  426. omap2430_hwmod_init();
  427. omap_hwmod_init_postsetup();
  428. omap_clk_soc_init = omap2430_dt_clk_init;
  429. rate_table = omap2430_rate_table;
  430. }
  431. void __init omap2430_init_late(void)
  432. {
  433. omap_pm_soc_init = omap2_pm_init;
  434. }
  435. #endif
  436. /*
  437. * Currently only board-omap3beagle.c should call this because of the
  438. * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
  439. */
  440. #ifdef CONFIG_ARCH_OMAP3
  441. void __init omap3_init_early(void)
  442. {
  443. omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
  444. omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
  445. OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
  446. omap2_control_base_init();
  447. omap3xxx_check_revision();
  448. omap3xxx_check_features();
  449. omap2_prcm_base_init();
  450. omap3xxx_voltagedomains_init();
  451. omap3xxx_powerdomains_init();
  452. omap3xxx_clockdomains_init();
  453. omap3xxx_hwmod_init();
  454. omap_hwmod_init_postsetup();
  455. omap_secure_init();
  456. }
  457. void __init omap3430_init_early(void)
  458. {
  459. omap3_init_early();
  460. omap_clk_soc_init = omap3430_dt_clk_init;
  461. }
  462. void __init omap35xx_init_early(void)
  463. {
  464. omap3_init_early();
  465. omap_clk_soc_init = omap3430_dt_clk_init;
  466. }
  467. void __init omap3630_init_early(void)
  468. {
  469. omap3_init_early();
  470. omap_clk_soc_init = omap3630_dt_clk_init;
  471. }
  472. void __init am35xx_init_early(void)
  473. {
  474. omap3_init_early();
  475. omap_clk_soc_init = am35xx_dt_clk_init;
  476. }
  477. void __init omap3_init_late(void)
  478. {
  479. omap_pm_soc_init = omap3_pm_init;
  480. }
  481. void __init ti81xx_init_late(void)
  482. {
  483. omap_pm_soc_init = omap_pm_nop_init;
  484. }
  485. #endif
  486. #ifdef CONFIG_SOC_TI81XX
  487. void __init ti814x_init_early(void)
  488. {
  489. omap2_set_globals_tap(TI814X_CLASS,
  490. OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
  491. omap2_control_base_init();
  492. omap3xxx_check_revision();
  493. ti81xx_check_features();
  494. omap2_prcm_base_init();
  495. omap3xxx_voltagedomains_init();
  496. omap3xxx_powerdomains_init();
  497. ti814x_clockdomains_init();
  498. dm814x_hwmod_init();
  499. omap_hwmod_init_postsetup();
  500. omap_clk_soc_init = dm814x_dt_clk_init;
  501. omap_secure_init();
  502. }
  503. void __init ti816x_init_early(void)
  504. {
  505. omap2_set_globals_tap(TI816X_CLASS,
  506. OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
  507. omap2_control_base_init();
  508. omap3xxx_check_revision();
  509. ti81xx_check_features();
  510. omap2_prcm_base_init();
  511. omap3xxx_voltagedomains_init();
  512. omap3xxx_powerdomains_init();
  513. ti816x_clockdomains_init();
  514. dm816x_hwmod_init();
  515. omap_hwmod_init_postsetup();
  516. omap_clk_soc_init = dm816x_dt_clk_init;
  517. omap_secure_init();
  518. }
  519. #endif
  520. #ifdef CONFIG_SOC_AM33XX
  521. void __init am33xx_init_early(void)
  522. {
  523. omap2_set_globals_tap(AM335X_CLASS,
  524. AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
  525. omap2_control_base_init();
  526. omap3xxx_check_revision();
  527. am33xx_check_features();
  528. omap2_prcm_base_init();
  529. am33xx_powerdomains_init();
  530. am33xx_clockdomains_init();
  531. omap_clk_soc_init = am33xx_dt_clk_init;
  532. omap_secure_init();
  533. }
  534. void __init am33xx_init_late(void)
  535. {
  536. omap_pm_soc_init = amx3_common_pm_init;
  537. }
  538. #endif
  539. #ifdef CONFIG_SOC_AM43XX
  540. void __init am43xx_init_early(void)
  541. {
  542. omap2_set_globals_tap(AM335X_CLASS,
  543. AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
  544. omap2_control_base_init();
  545. omap3xxx_check_revision();
  546. am33xx_check_features();
  547. omap2_prcm_base_init();
  548. am43xx_powerdomains_init();
  549. am43xx_clockdomains_init();
  550. omap_l2_cache_init();
  551. omap_clk_soc_init = am43xx_dt_clk_init;
  552. omap_secure_init();
  553. }
  554. void __init am43xx_init_late(void)
  555. {
  556. omap_pm_soc_init = amx3_common_pm_init;
  557. }
  558. #endif
  559. #ifdef CONFIG_ARCH_OMAP4
  560. void __init omap4430_init_early(void)
  561. {
  562. omap2_set_globals_tap(OMAP443X_CLASS,
  563. OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
  564. omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
  565. omap2_control_base_init();
  566. omap4xxx_check_revision();
  567. omap4xxx_check_features();
  568. omap2_prcm_base_init();
  569. omap4_sar_ram_init();
  570. omap4_mpuss_early_init();
  571. omap4_pm_init_early();
  572. omap44xx_voltagedomains_init();
  573. omap44xx_powerdomains_init();
  574. omap44xx_clockdomains_init();
  575. omap_l2_cache_init();
  576. omap_clk_soc_init = omap4xxx_dt_clk_init;
  577. omap_secure_init();
  578. }
  579. void __init omap4430_init_late(void)
  580. {
  581. omap_pm_soc_init = omap4_pm_init;
  582. }
  583. #endif
  584. #ifdef CONFIG_SOC_OMAP5
  585. void __init omap5_init_early(void)
  586. {
  587. omap2_set_globals_tap(OMAP54XX_CLASS,
  588. OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
  589. omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
  590. omap2_control_base_init();
  591. omap2_prcm_base_init();
  592. omap5xxx_check_revision();
  593. omap4_sar_ram_init();
  594. omap4_mpuss_early_init();
  595. omap4_pm_init_early();
  596. omap54xx_voltagedomains_init();
  597. omap54xx_powerdomains_init();
  598. omap54xx_clockdomains_init();
  599. omap_clk_soc_init = omap5xxx_dt_clk_init;
  600. omap_secure_init();
  601. }
  602. void __init omap5_init_late(void)
  603. {
  604. omap_pm_soc_init = omap4_pm_init;
  605. }
  606. #endif
  607. #ifdef CONFIG_SOC_DRA7XX
  608. void __init dra7xx_init_early(void)
  609. {
  610. omap2_set_globals_tap(DRA7XX_CLASS,
  611. OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
  612. omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
  613. omap2_control_base_init();
  614. omap4_pm_init_early();
  615. omap2_prcm_base_init();
  616. dra7xxx_check_revision();
  617. dra7xx_powerdomains_init();
  618. dra7xx_clockdomains_init();
  619. omap_clk_soc_init = dra7xx_dt_clk_init;
  620. omap_secure_init();
  621. }
  622. void __init dra7xx_init_late(void)
  623. {
  624. omap_pm_soc_init = omap4_pm_init;
  625. }
  626. #endif
  627. void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
  628. struct omap_sdrc_params *sdrc_cs1)
  629. {
  630. omap_sram_init();
  631. if (cpu_is_omap24xx() || omap3_has_sdrc()) {
  632. omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
  633. _omap2_init_reprogram_sdrc();
  634. }
  635. }
  636. int __init omap_clk_init(void)
  637. {
  638. int ret = 0;
  639. if (!omap_clk_soc_init)
  640. return 0;
  641. ti_clk_init_features();
  642. omap2_clk_setup_ll_ops();
  643. ret = omap_control_init();
  644. if (ret)
  645. return ret;
  646. ret = omap_prcm_init();
  647. if (ret)
  648. return ret;
  649. of_clk_init(NULL);
  650. ti_dt_clk_init_retry_clks();
  651. ti_dt_clockdomains_setup();
  652. ret = omap_clk_soc_init();
  653. return ret;
  654. }