id.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/mach-omap2/id.c
  4. *
  5. * OMAP2 CPU identification code
  6. *
  7. * Copyright (C) 2005 Nokia Corporation
  8. * Written by Tony Lindgren <[email protected]>
  9. *
  10. * Copyright (C) 2009-11 Texas Instruments
  11. * Added OMAP4 support - Santosh Shilimkar <[email protected]>
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/io.h>
  17. #include <linux/random.h>
  18. #include <linux/slab.h>
  19. #ifdef CONFIG_SOC_BUS
  20. #include <linux/sys_soc.h>
  21. #endif
  22. #include <asm/cputype.h>
  23. #include "common.h"
  24. #include "id.h"
  25. #include "soc.h"
  26. #include "control.h"
  27. #define OMAP4_SILICON_TYPE_STANDARD 0x01
  28. #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02
  29. #define OMAP_SOC_MAX_NAME_LENGTH 16
  30. static unsigned int omap_revision;
  31. static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
  32. static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
  33. u32 omap_features;
  34. unsigned int omap_rev(void)
  35. {
  36. return omap_revision;
  37. }
  38. EXPORT_SYMBOL(omap_rev);
  39. int omap_type(void)
  40. {
  41. static u32 val = OMAP2_DEVICETYPE_MASK;
  42. if (val < OMAP2_DEVICETYPE_MASK)
  43. return val;
  44. if (soc_is_omap24xx()) {
  45. val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
  46. } else if (soc_is_ti81xx()) {
  47. val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
  48. } else if (soc_is_am33xx() || soc_is_am43xx()) {
  49. val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
  50. } else if (soc_is_omap34xx()) {
  51. val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
  52. } else if (soc_is_omap44xx()) {
  53. val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
  54. } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
  55. val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
  56. val &= OMAP5_DEVICETYPE_MASK;
  57. val >>= 6;
  58. goto out;
  59. } else {
  60. pr_err("Cannot detect omap type!\n");
  61. goto out;
  62. }
  63. val &= OMAP2_DEVICETYPE_MASK;
  64. val >>= 8;
  65. out:
  66. return val;
  67. }
  68. EXPORT_SYMBOL(omap_type);
  69. /*----------------------------------------------------------------------------*/
  70. #define OMAP_TAP_IDCODE 0x0204
  71. #define OMAP_TAP_DIE_ID_0 0x0218
  72. #define OMAP_TAP_DIE_ID_1 0x021C
  73. #define OMAP_TAP_DIE_ID_2 0x0220
  74. #define OMAP_TAP_DIE_ID_3 0x0224
  75. #define OMAP_TAP_DIE_ID_44XX_0 0x0200
  76. #define OMAP_TAP_DIE_ID_44XX_1 0x0208
  77. #define OMAP_TAP_DIE_ID_44XX_2 0x020c
  78. #define OMAP_TAP_DIE_ID_44XX_3 0x0210
  79. #define read_tap_reg(reg) readl_relaxed(tap_base + (reg))
  80. struct omap_id {
  81. u16 hawkeye; /* Silicon type (Hawkeye id) */
  82. u8 dev; /* Device type from production_id reg */
  83. u32 type; /* Combined type id copied to omap_revision */
  84. };
  85. /* Register values to detect the OMAP version */
  86. static struct omap_id omap_ids[] __initdata = {
  87. { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
  88. { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
  89. { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
  90. { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
  91. { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
  92. { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
  93. };
  94. static void __iomem *tap_base;
  95. static u16 tap_prod_id;
  96. void omap_get_die_id(struct omap_die_id *odi)
  97. {
  98. if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
  99. odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
  100. odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
  101. odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
  102. odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
  103. return;
  104. }
  105. odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
  106. odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
  107. odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
  108. odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
  109. }
  110. static int __init omap_feed_randpool(void)
  111. {
  112. struct omap_die_id odi;
  113. /* Throw the die ID into the entropy pool at boot */
  114. omap_get_die_id(&odi);
  115. add_device_randomness(&odi, sizeof(odi));
  116. return 0;
  117. }
  118. omap_device_initcall(omap_feed_randpool);
  119. void __init omap2xxx_check_revision(void)
  120. {
  121. int i, j;
  122. u32 idcode, prod_id;
  123. u16 hawkeye;
  124. u8 dev_type, rev;
  125. struct omap_die_id odi;
  126. idcode = read_tap_reg(OMAP_TAP_IDCODE);
  127. prod_id = read_tap_reg(tap_prod_id);
  128. hawkeye = (idcode >> 12) & 0xffff;
  129. rev = (idcode >> 28) & 0x0f;
  130. dev_type = (prod_id >> 16) & 0x0f;
  131. omap_get_die_id(&odi);
  132. pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
  133. idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
  134. pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
  135. pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
  136. odi.id_1, (odi.id_1 >> 28) & 0xf);
  137. pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
  138. pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
  139. pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
  140. prod_id, dev_type);
  141. /* Check hawkeye ids */
  142. for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
  143. if (hawkeye == omap_ids[i].hawkeye)
  144. break;
  145. }
  146. if (i == ARRAY_SIZE(omap_ids)) {
  147. printk(KERN_ERR "Unknown OMAP CPU id\n");
  148. return;
  149. }
  150. for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
  151. if (dev_type == omap_ids[j].dev)
  152. break;
  153. }
  154. if (j == ARRAY_SIZE(omap_ids)) {
  155. pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
  156. omap_ids[i].type >> 16);
  157. j = i;
  158. }
  159. sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
  160. sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
  161. pr_info("%s", soc_name);
  162. if ((omap_rev() >> 8) & 0x0f)
  163. pr_cont("%s", soc_rev);
  164. pr_cont("\n");
  165. }
  166. #define OMAP3_SHOW_FEATURE(feat) \
  167. if (omap3_has_ ##feat()) \
  168. n += scnprintf(buf + n, sizeof(buf) - n, #feat " ");
  169. static void __init omap3_cpuinfo(void)
  170. {
  171. const char *cpu_name;
  172. char buf[64];
  173. int n = 0;
  174. memset(buf, 0, sizeof(buf));
  175. /*
  176. * OMAP3430 and OMAP3530 are assumed to be same.
  177. *
  178. * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
  179. * on available features. Upon detection, update the CPU id
  180. * and CPU class bits.
  181. */
  182. if (soc_is_omap3630()) {
  183. if (omap3_has_iva() && omap3_has_sgx()) {
  184. cpu_name = (omap3_has_isp()) ? "OMAP3630/DM3730" : "OMAP3621";
  185. } else if (omap3_has_iva()) {
  186. cpu_name = "DM3725";
  187. } else if (omap3_has_sgx()) {
  188. cpu_name = "OMAP3615/AM3715";
  189. } else {
  190. cpu_name = (omap3_has_isp()) ? "AM3703" : "OMAP3611";
  191. }
  192. } else if (soc_is_am35xx()) {
  193. cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
  194. } else if (soc_is_ti816x()) {
  195. cpu_name = "TI816X";
  196. } else if (soc_is_am335x()) {
  197. cpu_name = "AM335X";
  198. } else if (soc_is_am437x()) {
  199. cpu_name = "AM437x";
  200. } else if (soc_is_ti814x()) {
  201. cpu_name = "TI814X";
  202. } else if (omap3_has_iva() && omap3_has_sgx()) {
  203. /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
  204. cpu_name = "OMAP3430/3530";
  205. } else if (omap3_has_iva()) {
  206. cpu_name = "OMAP3525";
  207. } else if (omap3_has_sgx()) {
  208. cpu_name = "OMAP3515";
  209. } else {
  210. cpu_name = "OMAP3503";
  211. }
  212. scnprintf(soc_name, sizeof(soc_name), "%s", cpu_name);
  213. /* Print verbose information */
  214. n += scnprintf(buf, sizeof(buf) - n, "%s %s (", soc_name, soc_rev);
  215. OMAP3_SHOW_FEATURE(l2cache);
  216. OMAP3_SHOW_FEATURE(iva);
  217. OMAP3_SHOW_FEATURE(sgx);
  218. OMAP3_SHOW_FEATURE(neon);
  219. OMAP3_SHOW_FEATURE(isp);
  220. OMAP3_SHOW_FEATURE(192mhz_clk);
  221. if (*(buf + n - 1) == ' ')
  222. n--;
  223. n += scnprintf(buf + n, sizeof(buf) - n, ")\n");
  224. pr_info("%s", buf);
  225. }
  226. #define OMAP3_CHECK_FEATURE(status,feat) \
  227. if (((status & OMAP3_ ##feat## _MASK) \
  228. >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
  229. omap_features |= OMAP3_HAS_ ##feat; \
  230. }
  231. void __init omap3xxx_check_features(void)
  232. {
  233. u32 status;
  234. omap_features = 0;
  235. status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
  236. OMAP3_CHECK_FEATURE(status, L2CACHE);
  237. OMAP3_CHECK_FEATURE(status, IVA);
  238. OMAP3_CHECK_FEATURE(status, SGX);
  239. OMAP3_CHECK_FEATURE(status, NEON);
  240. OMAP3_CHECK_FEATURE(status, ISP);
  241. if (soc_is_omap3630())
  242. omap_features |= OMAP3_HAS_192MHZ_CLK;
  243. if (soc_is_omap3430() || soc_is_omap3630())
  244. omap_features |= OMAP3_HAS_IO_WAKEUP;
  245. if (soc_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
  246. omap_rev() == OMAP3430_REV_ES3_1_2)
  247. omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
  248. omap_features |= OMAP3_HAS_SDRC;
  249. /*
  250. * am35x fixups:
  251. * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
  252. * reserved and therefore return 0 when read. Unfortunately,
  253. * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
  254. * mean that a feature is present even though it isn't so clear
  255. * the incorrectly set feature bits.
  256. */
  257. if (soc_is_am35xx())
  258. omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
  259. /*
  260. * TODO: Get additional info (where applicable)
  261. * e.g. Size of L2 cache.
  262. */
  263. omap3_cpuinfo();
  264. }
  265. void __init omap4xxx_check_features(void)
  266. {
  267. u32 si_type;
  268. si_type =
  269. (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
  270. if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
  271. omap_features = OMAP4_HAS_PERF_SILICON;
  272. }
  273. void __init ti81xx_check_features(void)
  274. {
  275. omap_features = OMAP3_HAS_NEON;
  276. omap3_cpuinfo();
  277. }
  278. void __init am33xx_check_features(void)
  279. {
  280. u32 status;
  281. omap_features = OMAP3_HAS_NEON;
  282. status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
  283. if (status & AM33XX_SGX_MASK)
  284. omap_features |= OMAP3_HAS_SGX;
  285. omap3_cpuinfo();
  286. }
  287. void __init omap3xxx_check_revision(void)
  288. {
  289. const char *cpu_rev;
  290. u32 cpuid, idcode;
  291. u16 hawkeye;
  292. u8 rev;
  293. /*
  294. * We cannot access revision registers on ES1.0.
  295. * If the processor type is Cortex-A8 and the revision is 0x0
  296. * it means its Cortex r0p0 which is 3430 ES1.0.
  297. */
  298. cpuid = read_cpuid_id();
  299. if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
  300. omap_revision = OMAP3430_REV_ES1_0;
  301. cpu_rev = "1.0";
  302. return;
  303. }
  304. /*
  305. * Detection for 34xx ES2.0 and above can be done with just
  306. * hawkeye and rev. See TRM 1.5.2 Device Identification.
  307. * Note that rev does not map directly to our defined processor
  308. * revision numbers as ES1.0 uses value 0.
  309. */
  310. idcode = read_tap_reg(OMAP_TAP_IDCODE);
  311. hawkeye = (idcode >> 12) & 0xffff;
  312. rev = (idcode >> 28) & 0xff;
  313. switch (hawkeye) {
  314. case 0xb7ae:
  315. /* Handle 34xx/35xx devices */
  316. switch (rev) {
  317. case 0: /* Take care of early samples */
  318. case 1:
  319. omap_revision = OMAP3430_REV_ES2_0;
  320. cpu_rev = "2.0";
  321. break;
  322. case 2:
  323. omap_revision = OMAP3430_REV_ES2_1;
  324. cpu_rev = "2.1";
  325. break;
  326. case 3:
  327. omap_revision = OMAP3430_REV_ES3_0;
  328. cpu_rev = "3.0";
  329. break;
  330. case 4:
  331. omap_revision = OMAP3430_REV_ES3_1;
  332. cpu_rev = "3.1";
  333. break;
  334. case 7:
  335. default:
  336. /* Use the latest known revision as default */
  337. omap_revision = OMAP3430_REV_ES3_1_2;
  338. cpu_rev = "3.1.2";
  339. }
  340. break;
  341. case 0xb868:
  342. /*
  343. * Handle OMAP/AM 3505/3517 devices
  344. *
  345. * Set the device to be OMAP3517 here. Actual device
  346. * is identified later based on the features.
  347. */
  348. switch (rev) {
  349. case 0:
  350. omap_revision = AM35XX_REV_ES1_0;
  351. cpu_rev = "1.0";
  352. break;
  353. case 1:
  354. default:
  355. omap_revision = AM35XX_REV_ES1_1;
  356. cpu_rev = "1.1";
  357. }
  358. break;
  359. case 0xb891:
  360. /* Handle 36xx devices */
  361. switch(rev) {
  362. case 0: /* Take care of early samples */
  363. omap_revision = OMAP3630_REV_ES1_0;
  364. cpu_rev = "1.0";
  365. break;
  366. case 1:
  367. omap_revision = OMAP3630_REV_ES1_1;
  368. cpu_rev = "1.1";
  369. break;
  370. case 2:
  371. default:
  372. omap_revision = OMAP3630_REV_ES1_2;
  373. cpu_rev = "1.2";
  374. }
  375. break;
  376. case 0xb81e:
  377. switch (rev) {
  378. case 0:
  379. omap_revision = TI8168_REV_ES1_0;
  380. cpu_rev = "1.0";
  381. break;
  382. case 1:
  383. omap_revision = TI8168_REV_ES1_1;
  384. cpu_rev = "1.1";
  385. break;
  386. case 2:
  387. omap_revision = TI8168_REV_ES2_0;
  388. cpu_rev = "2.0";
  389. break;
  390. case 3:
  391. default:
  392. omap_revision = TI8168_REV_ES2_1;
  393. cpu_rev = "2.1";
  394. }
  395. break;
  396. case 0xb944:
  397. switch (rev) {
  398. case 0:
  399. omap_revision = AM335X_REV_ES1_0;
  400. cpu_rev = "1.0";
  401. break;
  402. case 1:
  403. omap_revision = AM335X_REV_ES2_0;
  404. cpu_rev = "2.0";
  405. break;
  406. case 2:
  407. default:
  408. omap_revision = AM335X_REV_ES2_1;
  409. cpu_rev = "2.1";
  410. break;
  411. }
  412. break;
  413. case 0xb98c:
  414. switch (rev) {
  415. case 0:
  416. omap_revision = AM437X_REV_ES1_0;
  417. cpu_rev = "1.0";
  418. break;
  419. case 1:
  420. omap_revision = AM437X_REV_ES1_1;
  421. cpu_rev = "1.1";
  422. break;
  423. case 2:
  424. default:
  425. omap_revision = AM437X_REV_ES1_2;
  426. cpu_rev = "1.2";
  427. break;
  428. }
  429. break;
  430. case 0xb8f2:
  431. case 0xb968:
  432. switch (rev) {
  433. case 0:
  434. case 1:
  435. omap_revision = TI8148_REV_ES1_0;
  436. cpu_rev = "1.0";
  437. break;
  438. case 2:
  439. omap_revision = TI8148_REV_ES2_0;
  440. cpu_rev = "2.0";
  441. break;
  442. case 3:
  443. default:
  444. omap_revision = TI8148_REV_ES2_1;
  445. cpu_rev = "2.1";
  446. break;
  447. }
  448. break;
  449. default:
  450. /* Unknown default to latest silicon rev as default */
  451. omap_revision = OMAP3630_REV_ES1_2;
  452. cpu_rev = "1.2";
  453. pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n",
  454. hawkeye);
  455. }
  456. sprintf(soc_rev, "ES%s", cpu_rev);
  457. }
  458. void __init omap4xxx_check_revision(void)
  459. {
  460. u32 idcode;
  461. u16 hawkeye;
  462. u8 rev;
  463. /*
  464. * The IC rev detection is done with hawkeye and rev.
  465. * Note that rev does not map directly to defined processor
  466. * revision numbers as ES1.0 uses value 0.
  467. */
  468. idcode = read_tap_reg(OMAP_TAP_IDCODE);
  469. hawkeye = (idcode >> 12) & 0xffff;
  470. rev = (idcode >> 28) & 0xf;
  471. /*
  472. * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
  473. * Use ARM register to detect the correct ES version
  474. */
  475. if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
  476. idcode = read_cpuid_id();
  477. rev = (idcode & 0xf) - 1;
  478. }
  479. switch (hawkeye) {
  480. case 0xb852:
  481. switch (rev) {
  482. case 0:
  483. omap_revision = OMAP4430_REV_ES1_0;
  484. break;
  485. case 1:
  486. default:
  487. omap_revision = OMAP4430_REV_ES2_0;
  488. }
  489. break;
  490. case 0xb95c:
  491. switch (rev) {
  492. case 3:
  493. omap_revision = OMAP4430_REV_ES2_1;
  494. break;
  495. case 4:
  496. omap_revision = OMAP4430_REV_ES2_2;
  497. break;
  498. case 6:
  499. default:
  500. omap_revision = OMAP4430_REV_ES2_3;
  501. }
  502. break;
  503. case 0xb94e:
  504. switch (rev) {
  505. case 0:
  506. omap_revision = OMAP4460_REV_ES1_0;
  507. break;
  508. case 2:
  509. default:
  510. omap_revision = OMAP4460_REV_ES1_1;
  511. break;
  512. }
  513. break;
  514. case 0xb975:
  515. switch (rev) {
  516. case 0:
  517. default:
  518. omap_revision = OMAP4470_REV_ES1_0;
  519. break;
  520. }
  521. break;
  522. default:
  523. /* Unknown default to latest silicon rev as default */
  524. omap_revision = OMAP4430_REV_ES2_3;
  525. }
  526. sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
  527. sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
  528. (omap_rev() >> 8) & 0xf);
  529. pr_info("%s %s\n", soc_name, soc_rev);
  530. }
  531. void __init omap5xxx_check_revision(void)
  532. {
  533. u32 idcode;
  534. u16 hawkeye;
  535. u8 rev;
  536. idcode = read_tap_reg(OMAP_TAP_IDCODE);
  537. hawkeye = (idcode >> 12) & 0xffff;
  538. rev = (idcode >> 28) & 0xff;
  539. switch (hawkeye) {
  540. case 0xb942:
  541. switch (rev) {
  542. case 0:
  543. /* No support for ES1.0 Test chip */
  544. BUG();
  545. case 1:
  546. default:
  547. omap_revision = OMAP5430_REV_ES2_0;
  548. }
  549. break;
  550. case 0xb998:
  551. switch (rev) {
  552. case 0:
  553. /* No support for ES1.0 Test chip */
  554. BUG();
  555. case 1:
  556. default:
  557. omap_revision = OMAP5432_REV_ES2_0;
  558. }
  559. break;
  560. default:
  561. /* Unknown default to latest silicon rev as default*/
  562. omap_revision = OMAP5430_REV_ES2_0;
  563. }
  564. sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
  565. sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
  566. pr_info("%s %s\n", soc_name, soc_rev);
  567. }
  568. void __init dra7xxx_check_revision(void)
  569. {
  570. u32 idcode;
  571. u16 hawkeye;
  572. u8 rev, package;
  573. struct omap_die_id odi;
  574. omap_get_die_id(&odi);
  575. package = (odi.id_2 >> 16) & 0x3;
  576. idcode = read_tap_reg(OMAP_TAP_IDCODE);
  577. hawkeye = (idcode >> 12) & 0xffff;
  578. rev = (idcode >> 28) & 0xff;
  579. switch (hawkeye) {
  580. case 0xbb50:
  581. switch (rev) {
  582. case 0:
  583. default:
  584. switch (package) {
  585. case 0x2:
  586. omap_revision = DRA762_ABZ_REV_ES1_0;
  587. break;
  588. case 0x3:
  589. omap_revision = DRA762_ACD_REV_ES1_0;
  590. break;
  591. default:
  592. omap_revision = DRA762_REV_ES1_0;
  593. break;
  594. }
  595. break;
  596. }
  597. break;
  598. case 0xb990:
  599. switch (rev) {
  600. case 0:
  601. omap_revision = DRA752_REV_ES1_0;
  602. break;
  603. case 1:
  604. omap_revision = DRA752_REV_ES1_1;
  605. break;
  606. case 2:
  607. default:
  608. omap_revision = DRA752_REV_ES2_0;
  609. break;
  610. }
  611. break;
  612. case 0xb9bc:
  613. switch (rev) {
  614. case 0:
  615. omap_revision = DRA722_REV_ES1_0;
  616. break;
  617. case 1:
  618. omap_revision = DRA722_REV_ES2_0;
  619. break;
  620. case 2:
  621. default:
  622. omap_revision = DRA722_REV_ES2_1;
  623. break;
  624. }
  625. break;
  626. default:
  627. /* Unknown default to latest silicon rev as default*/
  628. pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
  629. __func__, idcode, hawkeye, rev);
  630. omap_revision = DRA752_REV_ES2_0;
  631. }
  632. sprintf(soc_name, "DRA%03x", omap_rev() >> 16);
  633. sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
  634. (omap_rev() >> 8) & 0xf);
  635. pr_info("%s %s\n", soc_name, soc_rev);
  636. }
  637. /*
  638. * Set up things for map_io and processor detection later on. Gets called
  639. * pretty much first thing from board init. For multi-omap, this gets
  640. * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
  641. * detect the exact revision later on in omap2_detect_revision() once map_io
  642. * is done.
  643. */
  644. void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
  645. {
  646. omap_revision = class;
  647. tap_base = tap;
  648. /* XXX What is this intended to do? */
  649. if (soc_is_omap34xx())
  650. tap_prod_id = 0x0210;
  651. else
  652. tap_prod_id = 0x0208;
  653. }
  654. #ifdef CONFIG_SOC_BUS
  655. static const char * const omap_types[] = {
  656. [OMAP2_DEVICE_TYPE_TEST] = "TST",
  657. [OMAP2_DEVICE_TYPE_EMU] = "EMU",
  658. [OMAP2_DEVICE_TYPE_SEC] = "HS",
  659. [OMAP2_DEVICE_TYPE_GP] = "GP",
  660. [OMAP2_DEVICE_TYPE_BAD] = "BAD",
  661. };
  662. static const char * __init omap_get_family(void)
  663. {
  664. if (soc_is_omap24xx())
  665. return kasprintf(GFP_KERNEL, "OMAP2");
  666. else if (soc_is_omap34xx())
  667. return kasprintf(GFP_KERNEL, "OMAP3");
  668. else if (soc_is_omap44xx())
  669. return kasprintf(GFP_KERNEL, "OMAP4");
  670. else if (soc_is_omap54xx())
  671. return kasprintf(GFP_KERNEL, "OMAP5");
  672. else if (soc_is_am33xx() || soc_is_am335x())
  673. return kasprintf(GFP_KERNEL, "AM33xx");
  674. else if (soc_is_am43xx())
  675. return kasprintf(GFP_KERNEL, "AM43xx");
  676. else if (soc_is_dra7xx())
  677. return kasprintf(GFP_KERNEL, "DRA7");
  678. else
  679. return kasprintf(GFP_KERNEL, "Unknown");
  680. }
  681. static ssize_t
  682. type_show(struct device *dev, struct device_attribute *attr, char *buf)
  683. {
  684. return sprintf(buf, "%s\n", omap_types[omap_type()]);
  685. }
  686. static DEVICE_ATTR_RO(type);
  687. static struct attribute *omap_soc_attrs[] = {
  688. &dev_attr_type.attr,
  689. NULL
  690. };
  691. ATTRIBUTE_GROUPS(omap_soc);
  692. void __init omap_soc_device_init(void)
  693. {
  694. struct soc_device *soc_dev;
  695. struct soc_device_attribute *soc_dev_attr;
  696. soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
  697. if (!soc_dev_attr)
  698. return;
  699. soc_dev_attr->machine = soc_name;
  700. soc_dev_attr->family = omap_get_family();
  701. soc_dev_attr->revision = soc_rev;
  702. soc_dev_attr->custom_attr_group = omap_soc_groups[0];
  703. soc_dev = soc_device_register(soc_dev_attr);
  704. if (IS_ERR(soc_dev)) {
  705. kfree(soc_dev_attr);
  706. return;
  707. }
  708. }
  709. #endif /* CONFIG_SOC_BUS */