dma.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * OMAP2+ DMA driver
  4. *
  5. * Copyright (C) 2003 - 2008 Nokia Corporation
  6. * Author: Juha Yrjölä <[email protected]>
  7. * DMA channel linking for 1610 by Samuel Ortiz <[email protected]>
  8. * Graphics DMA and LCD DMA graphics tranformations
  9. * by Imre Deak <[email protected]>
  10. * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  11. * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12. *
  13. * Copyright (C) 2009 Texas Instruments
  14. * Added OMAP4 support - Santosh Shilimkar <[email protected]>
  15. *
  16. * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
  17. * Converted DMA library into platform driver
  18. * - G, Manjunath Kondaiah <[email protected]>
  19. */
  20. #include <linux/err.h>
  21. #include <linux/io.h>
  22. #include <linux/slab.h>
  23. #include <linux/module.h>
  24. #include <linux/init.h>
  25. #include <linux/device.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/dmaengine.h>
  28. #include <linux/of.h>
  29. #include <linux/omap-dma.h>
  30. #include "soc.h"
  31. #include "common.h"
  32. static const struct omap_dma_reg reg_map[] = {
  33. [REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
  34. [GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
  35. [IRQSTATUS_L0] = { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
  36. [IRQSTATUS_L1] = { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
  37. [IRQSTATUS_L2] = { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
  38. [IRQSTATUS_L3] = { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
  39. [IRQENABLE_L0] = { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
  40. [IRQENABLE_L1] = { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
  41. [IRQENABLE_L2] = { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
  42. [IRQENABLE_L3] = { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
  43. [SYSSTATUS] = { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
  44. [OCP_SYSCONFIG] = { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
  45. [CAPS_0] = { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
  46. [CAPS_2] = { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
  47. [CAPS_3] = { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
  48. [CAPS_4] = { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
  49. /* Common register offsets */
  50. [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
  51. [CLNK_CTRL] = { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
  52. [CICR] = { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
  53. [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
  54. [CSDP] = { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
  55. [CEN] = { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
  56. [CFN] = { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
  57. [CSEI] = { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
  58. [CSFI] = { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
  59. [CDEI] = { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
  60. [CDFI] = { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
  61. [CSAC] = { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
  62. [CDAC] = { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
  63. /* Channel specific register offsets */
  64. [CSSA] = { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
  65. [CDSA] = { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
  66. [CCEN] = { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
  67. [CCFN] = { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
  68. [COLOR] = { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
  69. /* OMAP4 specific registers */
  70. [CDP] = { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
  71. [CNDP] = { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
  72. [CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
  73. };
  74. static unsigned configure_dma_errata(void)
  75. {
  76. unsigned errata = 0;
  77. /*
  78. * Errata applicable for OMAP2430ES1.0 and all omap2420
  79. *
  80. * I.
  81. * Erratum ID: Not Available
  82. * Inter Frame DMA buffering issue DMA will wrongly
  83. * buffer elements if packing and bursting is enabled. This might
  84. * result in data gets stalled in FIFO at the end of the block.
  85. * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
  86. * guarantee no data will stay in the DMA FIFO in case inter frame
  87. * buffering occurs
  88. *
  89. * II.
  90. * Erratum ID: Not Available
  91. * DMA may hang when several channels are used in parallel
  92. * In the following configuration, DMA channel hanging can occur:
  93. * a. Channel i, hardware synchronized, is enabled
  94. * b. Another channel (Channel x), software synchronized, is enabled.
  95. * c. Channel i is disabled before end of transfer
  96. * d. Channel i is reenabled.
  97. * e. Steps 1 to 4 are repeated a certain number of times.
  98. * f. A third channel (Channel y), software synchronized, is enabled.
  99. * Channel x and Channel y may hang immediately after step 'f'.
  100. * Workaround:
  101. * For any channel used - make sure NextLCH_ID is set to the value j.
  102. */
  103. if (cpu_is_omap2420() || (cpu_is_omap2430() &&
  104. (omap_type() == OMAP2430_REV_ES1_0))) {
  105. SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
  106. SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
  107. }
  108. /*
  109. * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
  110. * after a transaction error.
  111. * Workaround: SW should explicitely disable the channel.
  112. */
  113. if (cpu_class_is_omap2())
  114. SET_DMA_ERRATA(DMA_ERRATA_i378);
  115. /*
  116. * Erratum ID: i541: sDMA FIFO draining does not finish
  117. * If sDMA channel is disabled on the fly, sDMA enters standby even
  118. * through FIFO Drain is still in progress
  119. * Workaround: Put sDMA in NoStandby more before a logical channel is
  120. * disabled, then put it back to SmartStandby right after the channel
  121. * finishes FIFO draining.
  122. */
  123. if (cpu_is_omap34xx())
  124. SET_DMA_ERRATA(DMA_ERRATA_i541);
  125. /*
  126. * Erratum ID: i88 : Special programming model needed to disable DMA
  127. * before end of block.
  128. * Workaround: software must ensure that the DMA is configured in No
  129. * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
  130. */
  131. if (omap_type() == OMAP3430_REV_ES1_0)
  132. SET_DMA_ERRATA(DMA_ERRATA_i88);
  133. /*
  134. * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
  135. * read before the DMA controller finished disabling the channel.
  136. */
  137. SET_DMA_ERRATA(DMA_ERRATA_3_3);
  138. /*
  139. * Erratum ID: Not Available
  140. * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
  141. * after secure sram context save and restore.
  142. * Work around: Hence we need to manually clear those IRQs to avoid
  143. * spurious interrupts. This affects only secure devices.
  144. */
  145. if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
  146. SET_DMA_ERRATA(DMA_ROMCODE_BUG);
  147. return errata;
  148. }
  149. static const struct dma_slave_map omap24xx_sdma_dt_map[] = {
  150. /* external DMA requests when tusb6010 is used */
  151. { "musb-hdrc.1.auto", "dmareq0", SDMA_FILTER_PARAM(2) },
  152. { "musb-hdrc.1.auto", "dmareq1", SDMA_FILTER_PARAM(3) },
  153. { "musb-hdrc.1.auto", "dmareq2", SDMA_FILTER_PARAM(14) }, /* OMAP2420 only */
  154. { "musb-hdrc.1.auto", "dmareq3", SDMA_FILTER_PARAM(15) }, /* OMAP2420 only */
  155. { "musb-hdrc.1.auto", "dmareq4", SDMA_FILTER_PARAM(16) }, /* OMAP2420 only */
  156. { "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */
  157. };
  158. static struct omap_dma_dev_attr dma_attr = {
  159. .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
  160. IS_CSSA_32 | IS_CDSA_32,
  161. .lch_count = 32,
  162. };
  163. struct omap_system_dma_plat_info dma_plat_info = {
  164. .reg_map = reg_map,
  165. .channel_stride = 0x60,
  166. .dma_attr = &dma_attr,
  167. };
  168. /* One time initializations */
  169. static int __init omap2_system_dma_init(void)
  170. {
  171. dma_plat_info.errata = configure_dma_errata();
  172. if (soc_is_omap24xx()) {
  173. /* DMA slave map for drivers not yet converted to DT */
  174. dma_plat_info.slave_map = omap24xx_sdma_dt_map;
  175. dma_plat_info.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
  176. }
  177. if (!soc_is_omap242x())
  178. dma_attr.dev_caps |= IS_RW_PRIORITY;
  179. if (soc_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
  180. dma_attr.dev_caps |= HS_CHANNELS_RESERVED;
  181. return 0;
  182. }
  183. omap_arch_initcall(omap2_system_dma_init);