Kconfig 6.8 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. menu "TI OMAP/AM/DM/DRA Family"
  3. depends on ARCH_MULTI_V6 || ARCH_MULTI_V7
  4. config OMAP_HWMOD
  5. bool
  6. config ARCH_OMAP2
  7. bool "TI OMAP2"
  8. depends on ARCH_MULTI_V6
  9. select ARCH_OMAP2PLUS
  10. select CPU_V6
  11. select OMAP_HWMOD
  12. select SOC_HAS_OMAP2_SDRC
  13. config ARCH_OMAP3
  14. bool "TI OMAP3"
  15. depends on ARCH_MULTI_V7
  16. select ARCH_OMAP2PLUS
  17. select ARM_CPU_SUSPEND
  18. select OMAP_HWMOD
  19. select OMAP_INTERCONNECT
  20. select PM_OPP
  21. select SOC_HAS_OMAP2_SDRC
  22. select ARM_ERRATA_430973
  23. config ARCH_OMAP4
  24. bool "TI OMAP4"
  25. depends on ARCH_MULTI_V7
  26. select ARCH_OMAP2PLUS
  27. select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
  28. select ARM_CPU_SUSPEND
  29. select ARM_ERRATA_720789
  30. select ARM_GIC
  31. select HAVE_ARM_SCU if SMP
  32. select HAVE_ARM_TWD if SMP
  33. select OMAP_INTERCONNECT
  34. select OMAP_INTERCONNECT_BARRIER
  35. select PL310_ERRATA_588369 if CACHE_L2X0
  36. select PL310_ERRATA_727915 if CACHE_L2X0
  37. select PM_OPP
  38. select PM if CPU_IDLE
  39. select ARM_ERRATA_754322
  40. select ARM_ERRATA_775420
  41. select OMAP_INTERCONNECT
  42. config SOC_OMAP5
  43. bool "TI OMAP5"
  44. depends on ARCH_MULTI_V7
  45. select ARCH_OMAP2PLUS
  46. select ARM_CPU_SUSPEND
  47. select ARM_GIC
  48. select HAVE_ARM_SCU if SMP
  49. select HAVE_ARM_ARCH_TIMER
  50. select ARM_ERRATA_798181 if SMP
  51. select OMAP_INTERCONNECT
  52. select OMAP_INTERCONNECT_BARRIER
  53. select PM_OPP
  54. select ZONE_DMA if ARM_LPAE
  55. config SOC_AM33XX
  56. bool "TI AM33XX"
  57. depends on ARCH_MULTI_V7
  58. select ARCH_OMAP2PLUS
  59. select ARM_CPU_SUSPEND
  60. config SOC_AM43XX
  61. bool "TI AM43x"
  62. depends on ARCH_MULTI_V7
  63. select ARCH_OMAP2PLUS
  64. select ARM_GIC
  65. select MACH_OMAP_GENERIC
  66. select HAVE_ARM_SCU
  67. select GENERIC_CLOCKEVENTS_BROADCAST
  68. select HAVE_ARM_TWD
  69. select ARM_ERRATA_754322
  70. select ARM_ERRATA_775420
  71. select OMAP_INTERCONNECT
  72. select ARM_CPU_SUSPEND
  73. config SOC_DRA7XX
  74. bool "TI DRA7XX"
  75. depends on ARCH_MULTI_V7
  76. select ARCH_OMAP2PLUS
  77. select ARM_CPU_SUSPEND
  78. select ARM_GIC
  79. select HAVE_ARM_SCU if SMP
  80. select HAVE_ARM_ARCH_TIMER
  81. select IRQ_CROSSBAR
  82. select ARM_ERRATA_798181 if SMP
  83. select OMAP_INTERCONNECT
  84. select OMAP_INTERCONNECT_BARRIER
  85. select PM_OPP
  86. select ZONE_DMA if ARM_LPAE
  87. select PINCTRL_TI_IODELAY if OF && PINCTRL
  88. config ARCH_OMAP2PLUS
  89. bool
  90. select ARCH_HAS_BANDGAP
  91. select ARCH_HAS_RESET_CONTROLLER
  92. select ARCH_OMAP
  93. select CLKSRC_MMIO
  94. select GENERIC_IRQ_CHIP
  95. select GPIOLIB
  96. select MACH_OMAP_GENERIC
  97. select MEMORY
  98. select MFD_SYSCON
  99. select OMAP_DM_SYSTIMER
  100. select OMAP_DM_TIMER
  101. select OMAP_GPMC
  102. select PINCTRL
  103. select PM
  104. select PM_GENERIC_DOMAINS
  105. select PM_GENERIC_DOMAINS_OF
  106. select RESET_CONTROLLER
  107. select SOC_BUS
  108. select TI_SYSC
  109. select OMAP_IRQCHIP
  110. select CLKSRC_TI_32K
  111. help
  112. Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
  113. config OMAP_INTERCONNECT_BARRIER
  114. bool
  115. select ARM_HEAVY_MB
  116. config ARCH_OMAP
  117. bool
  118. if ARCH_OMAP2PLUS
  119. menu "TI OMAP2/3/4 Specific Features"
  120. config ARCH_OMAP2PLUS_TYPICAL
  121. bool "Typical OMAP configuration"
  122. default y
  123. select AEABI
  124. select HIGHMEM
  125. select I2C
  126. select I2C_OMAP
  127. select MENELAUS if ARCH_OMAP2
  128. select NEON if CPU_V7
  129. select REGULATOR
  130. select REGULATOR_FIXED_VOLTAGE
  131. select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
  132. select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
  133. select VFP
  134. help
  135. Compile a kernel suitable for booting most boards
  136. config SOC_HAS_OMAP2_SDRC
  137. bool "OMAP2 SDRAM Controller support"
  138. config SOC_HAS_REALTIME_COUNTER
  139. bool "Real time free running counter"
  140. depends on SOC_OMAP5 || SOC_DRA7XX
  141. default y
  142. config POWER_AVS_OMAP
  143. bool "AVS(Adaptive Voltage Scaling) support for OMAP IP versions 1&2"
  144. depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
  145. select POWER_SUPPLY
  146. help
  147. Say Y to enable AVS(Adaptive Voltage Scaling)
  148. support on OMAP containing the version 1 or
  149. version 2 of the SmartReflex IP.
  150. V1 is the 65nm version used in OMAP3430.
  151. V2 is the update for the 45nm version of the IP used in OMAP3630
  152. and OMAP4430
  153. Please note, that by default SmartReflex is only
  154. initialized and not enabled. To enable the automatic voltage
  155. compensation for vdd mpu and vdd core from user space,
  156. user must write 1 to
  157. /debug/smartreflex/sr_<X>/autocomp,
  158. where X is mpu_iva or core for OMAP3.
  159. Optionally autocompensation can be enabled in the kernel
  160. by default during system init via the enable_on_init flag
  161. which an be passed as platform data to the smartreflex driver.
  162. config POWER_AVS_OMAP_CLASS3
  163. bool "Class 3 mode of Smartreflex Implementation"
  164. depends on POWER_AVS_OMAP && TWL4030_CORE
  165. help
  166. Say Y to enable Class 3 implementation of Smartreflex
  167. Class 3 implementation of Smartreflex employs continuous hardware
  168. voltage calibration.
  169. config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
  170. bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
  171. depends on ARCH_OMAP3 && PM
  172. help
  173. Without this option, L2 Auxiliary control register contents are
  174. lost during off-mode entry on HS/EMU devices. This feature
  175. requires support from PPA / boot-loader in HS/EMU devices, which
  176. currently does not exist by default.
  177. config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
  178. int "Service ID for the support routine to set L2 AUX control"
  179. depends on OMAP3_L2_AUX_SECURE_SAVE_RESTORE
  180. default 43
  181. help
  182. PPA routine service ID for setting L2 auxiliary control register.
  183. comment "OMAP Core Type"
  184. depends on ARCH_OMAP2
  185. config SOC_OMAP2420
  186. bool "OMAP2420 support"
  187. depends on ARCH_OMAP2
  188. default y
  189. select OMAP_DM_SYSTIMER
  190. select OMAP_DM_TIMER
  191. select SOC_HAS_OMAP2_SDRC
  192. config SOC_OMAP2430
  193. bool "OMAP2430 support"
  194. depends on ARCH_OMAP2
  195. default y
  196. select SOC_HAS_OMAP2_SDRC
  197. config SOC_OMAP3430
  198. bool "OMAP3430 support"
  199. depends on ARCH_OMAP3
  200. default y
  201. select SOC_HAS_OMAP2_SDRC
  202. config SOC_TI81XX
  203. bool "TI81XX support"
  204. depends on ARCH_OMAP3
  205. default y
  206. comment "OMAP Legacy Platform Data Board Type"
  207. depends on ARCH_OMAP2PLUS
  208. config MACH_OMAP_GENERIC
  209. bool
  210. config MACH_OMAP2_TUSB6010
  211. bool
  212. depends on ARCH_OMAP2 && SOC_OMAP2420
  213. default y if MACH_NOKIA_N8X0
  214. config MACH_NOKIA_N810
  215. bool
  216. config MACH_NOKIA_N810_WIMAX
  217. bool
  218. config MACH_NOKIA_N8X0
  219. bool "Nokia N800/N810"
  220. depends on SOC_OMAP2420
  221. default y
  222. select MACH_NOKIA_N810
  223. select MACH_NOKIA_N810_WIMAX
  224. config OMAP3_SDRC_AC_TIMING
  225. bool "Enable SDRC AC timing register changes"
  226. depends on ARCH_OMAP3
  227. help
  228. If you know that none of your system initiators will attempt to
  229. access SDRAM during CORE DVFS, select Y here. This should boost
  230. SDRAM performance at lower CORE OPPs. There are relatively few
  231. users who will wish to say yes at this point - almost everyone will
  232. wish to say no. Selecting yes without understanding what is
  233. going on could result in system crashes;
  234. endmenu
  235. endif
  236. config OMAP5_ERRATA_801819
  237. bool "Errata 801819: An eviction from L1 data cache might stall indefinitely"
  238. depends on SOC_OMAP5 || SOC_DRA7XX
  239. help
  240. A livelock can occur in the L2 cache arbitration that might prevent
  241. a snoop from completing. Under certain conditions this can cause the
  242. system to deadlock.
  243. endmenu