usb.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Platform level USB initialization for FS USB OTG controller on omap1
  4. *
  5. * Copyright (C) 2004 Texas Instruments, Inc.
  6. */
  7. #include <linux/module.h>
  8. #include <linux/kernel.h>
  9. #include <linux/init.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/dma-map-ops.h>
  12. #include <linux/io.h>
  13. #include <linux/delay.h>
  14. #include <linux/soc/ti/omap1-io.h>
  15. #include <asm/irq.h>
  16. #include "hardware.h"
  17. #include "mux.h"
  18. #include "usb.h"
  19. #include "common.h"
  20. /* These routines should handle the standard chip-specific modes
  21. * for usb0/1/2 ports, covering basic mux and transceiver setup.
  22. *
  23. * Some board-*.c files will need to set up additional mux options,
  24. * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup.
  25. */
  26. /* TESTED ON:
  27. * - 1611B H2 (with usb1 mini-AB) using standard Mini-B or OTG cables
  28. * - 5912 OSK OHCI (with usb0 standard-A), standard A-to-B cables
  29. * - 5912 OSK UDC, with *nonstandard* A-to-A cable
  30. * - 1510 Innovator UDC with bundled usb0 cable
  31. * - 1510 Innovator OHCI with bundled usb1/usb2 cable
  32. * - 1510 Innovator OHCI with custom usb0 cable, feeding 5V VBUS
  33. * - 1710 custom development board using alternate pin group
  34. * - 1710 H3 (with usb1 mini-AB) using standard Mini-B or OTG cables
  35. */
  36. #define INT_USB_IRQ_GEN IH2_BASE + 20
  37. #define INT_USB_IRQ_NISO IH2_BASE + 30
  38. #define INT_USB_IRQ_ISO IH2_BASE + 29
  39. #define INT_USB_IRQ_HGEN INT_USB_HHC_1
  40. #define INT_USB_IRQ_OTG IH2_BASE + 8
  41. #ifdef CONFIG_ARCH_OMAP_OTG
  42. static void __init
  43. omap_otg_init(struct omap_usb_config *config)
  44. {
  45. u32 syscon;
  46. int alt_pingroup = 0;
  47. u16 w;
  48. /* NOTE: no bus or clock setup (yet?) */
  49. syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
  50. if (!(syscon & OTG_RESET_DONE))
  51. pr_debug("USB resets not complete?\n");
  52. //omap_writew(0, OTG_IRQ_EN);
  53. /* pin muxing and transceiver pinouts */
  54. if (config->pins[0] > 2) /* alt pingroup 2 */
  55. alt_pingroup = 1;
  56. syscon |= config->usb0_init(config->pins[0], is_usb0_device(config));
  57. syscon |= config->usb1_init(config->pins[1]);
  58. syscon |= config->usb2_init(config->pins[2], alt_pingroup);
  59. pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
  60. omap_writel(syscon, OTG_SYSCON_1);
  61. syscon = config->hmc_mode;
  62. syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
  63. #ifdef CONFIG_USB_OTG
  64. if (config->otg)
  65. syscon |= OTG_EN;
  66. #endif
  67. pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
  68. omap_readl(USB_TRANSCEIVER_CTRL));
  69. pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
  70. omap_writel(syscon, OTG_SYSCON_2);
  71. printk("USB: hmc %d", config->hmc_mode);
  72. if (!alt_pingroup)
  73. pr_cont(", usb2 alt %d wires", config->pins[2]);
  74. else if (config->pins[0])
  75. pr_cont(", usb0 %d wires%s", config->pins[0],
  76. is_usb0_device(config) ? " (dev)" : "");
  77. if (config->pins[1])
  78. pr_cont(", usb1 %d wires", config->pins[1]);
  79. if (!alt_pingroup && config->pins[2])
  80. pr_cont(", usb2 %d wires", config->pins[2]);
  81. if (config->otg)
  82. pr_cont(", Mini-AB on usb%d", config->otg - 1);
  83. pr_cont("\n");
  84. /* leave USB clocks/controllers off until needed */
  85. w = omap_readw(ULPD_SOFT_REQ);
  86. w &= ~SOFT_USB_CLK_REQ;
  87. omap_writew(w, ULPD_SOFT_REQ);
  88. w = omap_readw(ULPD_CLOCK_CTRL);
  89. w &= ~USB_MCLK_EN;
  90. w |= DIS_USB_PVCI_CLK;
  91. omap_writew(w, ULPD_CLOCK_CTRL);
  92. syscon = omap_readl(OTG_SYSCON_1);
  93. syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
  94. #if IS_ENABLED(CONFIG_USB_OMAP)
  95. if (config->otg || config->register_dev) {
  96. struct platform_device *udc_device = config->udc_device;
  97. int status;
  98. syscon &= ~DEV_IDLE_EN;
  99. udc_device->dev.platform_data = config;
  100. status = platform_device_register(udc_device);
  101. if (status)
  102. pr_debug("can't register UDC device, %d\n", status);
  103. }
  104. #endif
  105. #if IS_ENABLED(CONFIG_USB_OHCI_HCD)
  106. if (config->otg || config->register_host) {
  107. struct platform_device *ohci_device = config->ohci_device;
  108. int status;
  109. syscon &= ~HST_IDLE_EN;
  110. ohci_device->dev.platform_data = config;
  111. status = platform_device_register(ohci_device);
  112. if (status)
  113. pr_debug("can't register OHCI device, %d\n", status);
  114. }
  115. #endif
  116. #ifdef CONFIG_USB_OTG
  117. if (config->otg) {
  118. struct platform_device *otg_device = config->otg_device;
  119. int status;
  120. syscon &= ~OTG_IDLE_EN;
  121. otg_device->dev.platform_data = config;
  122. status = platform_device_register(otg_device);
  123. if (status)
  124. pr_debug("can't register OTG device, %d\n", status);
  125. }
  126. #endif
  127. pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
  128. omap_writel(syscon, OTG_SYSCON_1);
  129. }
  130. #else
  131. static void omap_otg_init(struct omap_usb_config *config) {}
  132. #endif
  133. #if IS_ENABLED(CONFIG_USB_OMAP)
  134. static struct resource udc_resources[] = {
  135. /* order is significant! */
  136. { /* registers */
  137. .start = UDC_BASE,
  138. .end = UDC_BASE + 0xff,
  139. .flags = IORESOURCE_MEM,
  140. }, { /* general IRQ */
  141. .start = INT_USB_IRQ_GEN,
  142. .flags = IORESOURCE_IRQ,
  143. }, { /* PIO IRQ */
  144. .start = INT_USB_IRQ_NISO,
  145. .flags = IORESOURCE_IRQ,
  146. }, { /* SOF IRQ */
  147. .start = INT_USB_IRQ_ISO,
  148. .flags = IORESOURCE_IRQ,
  149. },
  150. };
  151. static u64 udc_dmamask = ~(u32)0;
  152. static struct platform_device udc_device = {
  153. .name = "omap_udc",
  154. .id = -1,
  155. .dev = {
  156. .dma_mask = &udc_dmamask,
  157. .coherent_dma_mask = 0xffffffff,
  158. },
  159. .num_resources = ARRAY_SIZE(udc_resources),
  160. .resource = udc_resources,
  161. };
  162. static inline void udc_device_init(struct omap_usb_config *pdata)
  163. {
  164. /* IRQ numbers for omap7xx */
  165. if(cpu_is_omap7xx()) {
  166. udc_resources[1].start = INT_7XX_USB_GENI;
  167. udc_resources[2].start = INT_7XX_USB_NON_ISO;
  168. udc_resources[3].start = INT_7XX_USB_ISO;
  169. }
  170. pdata->udc_device = &udc_device;
  171. }
  172. #else
  173. static inline void udc_device_init(struct omap_usb_config *pdata)
  174. {
  175. }
  176. #endif
  177. /* The dmamask must be set for OHCI to work */
  178. static u64 ohci_dmamask = ~(u32)0;
  179. static struct resource ohci_resources[] = {
  180. {
  181. .start = OMAP_OHCI_BASE,
  182. .end = OMAP_OHCI_BASE + 0xff,
  183. .flags = IORESOURCE_MEM,
  184. },
  185. {
  186. .start = INT_USB_IRQ_HGEN,
  187. .flags = IORESOURCE_IRQ,
  188. },
  189. };
  190. static struct platform_device ohci_device = {
  191. .name = "ohci",
  192. .id = -1,
  193. .dev = {
  194. .dma_mask = &ohci_dmamask,
  195. .coherent_dma_mask = 0xffffffff,
  196. },
  197. .num_resources = ARRAY_SIZE(ohci_resources),
  198. .resource = ohci_resources,
  199. };
  200. static inline void ohci_device_init(struct omap_usb_config *pdata)
  201. {
  202. if (!IS_ENABLED(CONFIG_USB_OHCI_HCD))
  203. return;
  204. if (cpu_is_omap7xx())
  205. ohci_resources[1].start = INT_7XX_USB_HHC_1;
  206. pdata->ohci_device = &ohci_device;
  207. pdata->ocpi_enable = &ocpi_enable;
  208. }
  209. #if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
  210. static struct resource otg_resources[] = {
  211. /* order is significant! */
  212. {
  213. .start = OTG_BASE,
  214. .end = OTG_BASE + 0xff,
  215. .flags = IORESOURCE_MEM,
  216. }, {
  217. .start = INT_USB_IRQ_OTG,
  218. .flags = IORESOURCE_IRQ,
  219. },
  220. };
  221. static struct platform_device otg_device = {
  222. .name = "omap_otg",
  223. .id = -1,
  224. .num_resources = ARRAY_SIZE(otg_resources),
  225. .resource = otg_resources,
  226. };
  227. static inline void otg_device_init(struct omap_usb_config *pdata)
  228. {
  229. if (cpu_is_omap7xx())
  230. otg_resources[1].start = INT_7XX_USB_OTG;
  231. pdata->otg_device = &otg_device;
  232. }
  233. #else
  234. static inline void otg_device_init(struct omap_usb_config *pdata)
  235. {
  236. }
  237. #endif
  238. static u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device)
  239. {
  240. u32 syscon1 = 0;
  241. if (nwires == 0) {
  242. if (!cpu_is_omap15xx()) {
  243. u32 l;
  244. /* pulldown D+/D- */
  245. l = omap_readl(USB_TRANSCEIVER_CTRL);
  246. l &= ~(3 << 1);
  247. omap_writel(l, USB_TRANSCEIVER_CTRL);
  248. }
  249. return 0;
  250. }
  251. if (is_device) {
  252. if (cpu_is_omap7xx()) {
  253. omap_cfg_reg(AA17_7XX_USB_DM);
  254. omap_cfg_reg(W16_7XX_USB_PU_EN);
  255. omap_cfg_reg(W17_7XX_USB_VBUSI);
  256. omap_cfg_reg(W18_7XX_USB_DMCK_OUT);
  257. omap_cfg_reg(W19_7XX_USB_DCRST);
  258. } else
  259. omap_cfg_reg(W4_USB_PUEN);
  260. }
  261. if (nwires == 2) {
  262. u32 l;
  263. // omap_cfg_reg(P9_USB_DP);
  264. // omap_cfg_reg(R8_USB_DM);
  265. if (cpu_is_omap15xx()) {
  266. /* This works on 1510-Innovator */
  267. return 0;
  268. }
  269. /* NOTES:
  270. * - peripheral should configure VBUS detection!
  271. * - only peripherals may use the internal D+/D- pulldowns
  272. * - OTG support on this port not yet written
  273. */
  274. /* Don't do this for omap7xx -- it causes USB to not work correctly */
  275. if (!cpu_is_omap7xx()) {
  276. l = omap_readl(USB_TRANSCEIVER_CTRL);
  277. l &= ~(7 << 4);
  278. if (!is_device)
  279. l |= (3 << 1);
  280. omap_writel(l, USB_TRANSCEIVER_CTRL);
  281. }
  282. return 3 << 16;
  283. }
  284. /* alternate pin config, external transceiver */
  285. if (cpu_is_omap15xx()) {
  286. printk(KERN_ERR "no usb0 alt pin config on 15xx\n");
  287. return 0;
  288. }
  289. omap_cfg_reg(V6_USB0_TXD);
  290. omap_cfg_reg(W9_USB0_TXEN);
  291. omap_cfg_reg(W5_USB0_SE0);
  292. if (nwires != 3)
  293. omap_cfg_reg(Y5_USB0_RCV);
  294. /* NOTE: SPEED and SUSP aren't configured here. OTG hosts
  295. * may be able to use I2C requests to set those bits along
  296. * with VBUS switching and overcurrent detection.
  297. */
  298. if (nwires != 6) {
  299. u32 l;
  300. l = omap_readl(USB_TRANSCEIVER_CTRL);
  301. l &= ~CONF_USB2_UNI_R;
  302. omap_writel(l, USB_TRANSCEIVER_CTRL);
  303. }
  304. switch (nwires) {
  305. case 3:
  306. syscon1 = 2;
  307. break;
  308. case 4:
  309. syscon1 = 1;
  310. break;
  311. case 6:
  312. syscon1 = 3;
  313. {
  314. u32 l;
  315. omap_cfg_reg(AA9_USB0_VP);
  316. omap_cfg_reg(R9_USB0_VM);
  317. l = omap_readl(USB_TRANSCEIVER_CTRL);
  318. l |= CONF_USB2_UNI_R;
  319. omap_writel(l, USB_TRANSCEIVER_CTRL);
  320. }
  321. break;
  322. default:
  323. printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
  324. 0, nwires);
  325. }
  326. return syscon1 << 16;
  327. }
  328. static u32 __init omap1_usb1_init(unsigned nwires)
  329. {
  330. u32 syscon1 = 0;
  331. if (!cpu_is_omap15xx() && nwires != 6) {
  332. u32 l;
  333. l = omap_readl(USB_TRANSCEIVER_CTRL);
  334. l &= ~CONF_USB1_UNI_R;
  335. omap_writel(l, USB_TRANSCEIVER_CTRL);
  336. }
  337. if (nwires == 0)
  338. return 0;
  339. /* external transceiver */
  340. omap_cfg_reg(USB1_TXD);
  341. omap_cfg_reg(USB1_TXEN);
  342. if (nwires != 3)
  343. omap_cfg_reg(USB1_RCV);
  344. if (cpu_is_omap15xx()) {
  345. omap_cfg_reg(USB1_SEO);
  346. omap_cfg_reg(USB1_SPEED);
  347. // SUSP
  348. } else if (cpu_is_omap1610() || cpu_is_omap5912()) {
  349. omap_cfg_reg(W13_1610_USB1_SE0);
  350. omap_cfg_reg(R13_1610_USB1_SPEED);
  351. // SUSP
  352. } else if (cpu_is_omap1710()) {
  353. omap_cfg_reg(R13_1710_USB1_SE0);
  354. // SUSP
  355. } else {
  356. pr_debug("usb%d cpu unrecognized\n", 1);
  357. return 0;
  358. }
  359. switch (nwires) {
  360. case 2:
  361. goto bad;
  362. case 3:
  363. syscon1 = 2;
  364. break;
  365. case 4:
  366. syscon1 = 1;
  367. break;
  368. case 6:
  369. syscon1 = 3;
  370. omap_cfg_reg(USB1_VP);
  371. omap_cfg_reg(USB1_VM);
  372. if (!cpu_is_omap15xx()) {
  373. u32 l;
  374. l = omap_readl(USB_TRANSCEIVER_CTRL);
  375. l |= CONF_USB1_UNI_R;
  376. omap_writel(l, USB_TRANSCEIVER_CTRL);
  377. }
  378. break;
  379. default:
  380. bad:
  381. printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
  382. 1, nwires);
  383. }
  384. return syscon1 << 20;
  385. }
  386. static u32 __init omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
  387. {
  388. u32 syscon1 = 0;
  389. /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
  390. if (alt_pingroup || nwires == 0)
  391. return 0;
  392. if (!cpu_is_omap15xx() && nwires != 6) {
  393. u32 l;
  394. l = omap_readl(USB_TRANSCEIVER_CTRL);
  395. l &= ~CONF_USB2_UNI_R;
  396. omap_writel(l, USB_TRANSCEIVER_CTRL);
  397. }
  398. /* external transceiver */
  399. if (cpu_is_omap15xx()) {
  400. omap_cfg_reg(USB2_TXD);
  401. omap_cfg_reg(USB2_TXEN);
  402. omap_cfg_reg(USB2_SEO);
  403. if (nwires != 3)
  404. omap_cfg_reg(USB2_RCV);
  405. /* there is no USB2_SPEED */
  406. } else if (cpu_is_omap16xx()) {
  407. omap_cfg_reg(V6_USB2_TXD);
  408. omap_cfg_reg(W9_USB2_TXEN);
  409. omap_cfg_reg(W5_USB2_SE0);
  410. if (nwires != 3)
  411. omap_cfg_reg(Y5_USB2_RCV);
  412. // FIXME omap_cfg_reg(USB2_SPEED);
  413. } else {
  414. pr_debug("usb%d cpu unrecognized\n", 1);
  415. return 0;
  416. }
  417. // omap_cfg_reg(USB2_SUSP);
  418. switch (nwires) {
  419. case 2:
  420. goto bad;
  421. case 3:
  422. syscon1 = 2;
  423. break;
  424. case 4:
  425. syscon1 = 1;
  426. break;
  427. case 5:
  428. goto bad;
  429. case 6:
  430. syscon1 = 3;
  431. if (cpu_is_omap15xx()) {
  432. omap_cfg_reg(USB2_VP);
  433. omap_cfg_reg(USB2_VM);
  434. } else {
  435. u32 l;
  436. omap_cfg_reg(AA9_USB2_VP);
  437. omap_cfg_reg(R9_USB2_VM);
  438. l = omap_readl(USB_TRANSCEIVER_CTRL);
  439. l |= CONF_USB2_UNI_R;
  440. omap_writel(l, USB_TRANSCEIVER_CTRL);
  441. }
  442. break;
  443. default:
  444. bad:
  445. printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
  446. 2, nwires);
  447. }
  448. return syscon1 << 24;
  449. }
  450. #ifdef CONFIG_ARCH_OMAP15XX
  451. /* OMAP-1510 OHCI has its own MMU for DMA */
  452. #define OMAP1510_LB_MEMSIZE 32 /* Should be same as SDRAM size */
  453. #define OMAP1510_LB_CLOCK_DIV 0xfffec10c
  454. #define OMAP1510_LB_MMU_CTL 0xfffec208
  455. #define OMAP1510_LB_MMU_LCK 0xfffec224
  456. #define OMAP1510_LB_MMU_LD_TLB 0xfffec228
  457. #define OMAP1510_LB_MMU_CAM_H 0xfffec22c
  458. #define OMAP1510_LB_MMU_CAM_L 0xfffec230
  459. #define OMAP1510_LB_MMU_RAM_H 0xfffec234
  460. #define OMAP1510_LB_MMU_RAM_L 0xfffec238
  461. /*
  462. * Bus address is physical address, except for OMAP-1510 Local Bus.
  463. * OMAP-1510 bus address is translated into a Local Bus address if the
  464. * OMAP bus type is lbus.
  465. */
  466. #define OMAP1510_LB_OFFSET UL(0x30000000)
  467. /*
  468. * OMAP-1510 specific Local Bus clock on/off
  469. */
  470. static int omap_1510_local_bus_power(int on)
  471. {
  472. if (on) {
  473. omap_writel((1 << 1) | (1 << 0), OMAP1510_LB_MMU_CTL);
  474. udelay(200);
  475. } else {
  476. omap_writel(0, OMAP1510_LB_MMU_CTL);
  477. }
  478. return 0;
  479. }
  480. /*
  481. * OMAP-1510 specific Local Bus initialization
  482. * NOTE: This assumes 32MB memory size in OMAP1510LB_MEMSIZE.
  483. * See also arch/mach-omap/memory.h for __virt_to_dma() and
  484. * __dma_to_virt() which need to match with the physical
  485. * Local Bus address below.
  486. */
  487. static int omap_1510_local_bus_init(void)
  488. {
  489. unsigned int tlb;
  490. unsigned long lbaddr, physaddr;
  491. omap_writel((omap_readl(OMAP1510_LB_CLOCK_DIV) & 0xfffffff8) | 0x4,
  492. OMAP1510_LB_CLOCK_DIV);
  493. /* Configure the Local Bus MMU table */
  494. for (tlb = 0; tlb < OMAP1510_LB_MEMSIZE; tlb++) {
  495. lbaddr = tlb * 0x00100000 + OMAP1510_LB_OFFSET;
  496. physaddr = tlb * 0x00100000 + PHYS_OFFSET;
  497. omap_writel((lbaddr & 0x0fffffff) >> 22, OMAP1510_LB_MMU_CAM_H);
  498. omap_writel(((lbaddr & 0x003ffc00) >> 6) | 0xc,
  499. OMAP1510_LB_MMU_CAM_L);
  500. omap_writel(physaddr >> 16, OMAP1510_LB_MMU_RAM_H);
  501. omap_writel((physaddr & 0x0000fc00) | 0x300, OMAP1510_LB_MMU_RAM_L);
  502. omap_writel(tlb << 4, OMAP1510_LB_MMU_LCK);
  503. omap_writel(0x1, OMAP1510_LB_MMU_LD_TLB);
  504. }
  505. /* Enable the walking table */
  506. omap_writel(omap_readl(OMAP1510_LB_MMU_CTL) | (1 << 3), OMAP1510_LB_MMU_CTL);
  507. udelay(200);
  508. return 0;
  509. }
  510. static void omap_1510_local_bus_reset(void)
  511. {
  512. omap_1510_local_bus_power(1);
  513. omap_1510_local_bus_init();
  514. }
  515. /* ULPD_DPLL_CTRL */
  516. #define DPLL_IOB (1 << 13)
  517. #define DPLL_PLL_ENABLE (1 << 4)
  518. #define DPLL_LOCK (1 << 0)
  519. /* ULPD_APLL_CTRL */
  520. #define APLL_NDPLL_SWITCH (1 << 0)
  521. static void __init omap_1510_usb_init(struct omap_usb_config *config)
  522. {
  523. unsigned int val;
  524. u16 w;
  525. config->usb0_init(config->pins[0], is_usb0_device(config));
  526. config->usb1_init(config->pins[1]);
  527. config->usb2_init(config->pins[2], 0);
  528. val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1);
  529. val |= (config->hmc_mode << 1);
  530. omap_writel(val, MOD_CONF_CTRL_0);
  531. printk("USB: hmc %d", config->hmc_mode);
  532. if (config->pins[0])
  533. pr_cont(", usb0 %d wires%s", config->pins[0],
  534. is_usb0_device(config) ? " (dev)" : "");
  535. if (config->pins[1])
  536. pr_cont(", usb1 %d wires", config->pins[1]);
  537. if (config->pins[2])
  538. pr_cont(", usb2 %d wires", config->pins[2]);
  539. pr_cont("\n");
  540. /* use DPLL for 48 MHz function clock */
  541. pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL),
  542. omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
  543. w = omap_readw(ULPD_APLL_CTRL);
  544. w &= ~APLL_NDPLL_SWITCH;
  545. omap_writew(w, ULPD_APLL_CTRL);
  546. w = omap_readw(ULPD_DPLL_CTRL);
  547. w |= DPLL_IOB | DPLL_PLL_ENABLE;
  548. omap_writew(w, ULPD_DPLL_CTRL);
  549. w = omap_readw(ULPD_SOFT_REQ);
  550. w |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
  551. omap_writew(w, ULPD_SOFT_REQ);
  552. while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
  553. cpu_relax();
  554. #if IS_ENABLED(CONFIG_USB_OMAP)
  555. if (config->register_dev) {
  556. int status;
  557. udc_device.dev.platform_data = config;
  558. status = platform_device_register(&udc_device);
  559. if (status)
  560. pr_debug("can't register UDC device, %d\n", status);
  561. /* udc driver gates 48MHz by D+ pullup */
  562. }
  563. #endif
  564. if (IS_ENABLED(CONFIG_USB_OHCI_HCD) && config->register_host) {
  565. int status;
  566. ohci_device.dev.platform_data = config;
  567. dma_direct_set_offset(&ohci_device.dev, PHYS_OFFSET,
  568. OMAP1510_LB_OFFSET, (u64)-1);
  569. status = platform_device_register(&ohci_device);
  570. if (status)
  571. pr_debug("can't register OHCI device, %d\n", status);
  572. /* hcd explicitly gates 48MHz */
  573. config->lb_reset = omap_1510_local_bus_reset;
  574. }
  575. }
  576. #else
  577. static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
  578. #endif
  579. void __init omap1_usb_init(struct omap_usb_config *_pdata)
  580. {
  581. struct omap_usb_config *pdata;
  582. pdata = kmemdup(_pdata, sizeof(*pdata), GFP_KERNEL);
  583. if (!pdata)
  584. return;
  585. pdata->usb0_init = omap1_usb0_init;
  586. pdata->usb1_init = omap1_usb1_init;
  587. pdata->usb2_init = omap1_usb2_init;
  588. udc_device_init(pdata);
  589. ohci_device_init(pdata);
  590. otg_device_init(pdata);
  591. if (cpu_is_omap7xx() || cpu_is_omap16xx())
  592. omap_otg_init(pdata);
  593. else if (cpu_is_omap15xx())
  594. omap_1510_usb_init(pdata);
  595. else
  596. printk(KERN_ERR "USB: No init for your chip yet\n");
  597. }