time.c 6.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234
  1. /*
  2. * linux/arch/arm/mach-omap1/time.c
  3. *
  4. * OMAP Timers
  5. *
  6. * Copyright (C) 2004 Nokia Corporation
  7. * Partial timer rewrite and additional dynamic tick timer support by
  8. * Tony Lindgen <[email protected]> and
  9. * Tuukka Tikkanen <[email protected]>
  10. *
  11. * MPU timer code based on the older MPU timer code for OMAP
  12. * Copyright (C) 2000 RidgeRun, Inc.
  13. * Author: Greg Lonnon <[email protected]>
  14. *
  15. * This program is free software; you can redistribute it and/or modify it
  16. * under the terms of the GNU General Public License as published by the
  17. * Free Software Foundation; either version 2 of the License, or (at your
  18. * option) any later version.
  19. *
  20. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  21. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  22. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  23. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  26. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  27. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30. *
  31. * You should have received a copy of the GNU General Public License along
  32. * with this program; if not, write to the Free Software Foundation, Inc.,
  33. * 675 Mass Ave, Cambridge, MA 02139, USA.
  34. */
  35. #include <linux/kernel.h>
  36. #include <linux/init.h>
  37. #include <linux/delay.h>
  38. #include <linux/interrupt.h>
  39. #include <linux/spinlock.h>
  40. #include <linux/clk.h>
  41. #include <linux/err.h>
  42. #include <linux/clocksource.h>
  43. #include <linux/clockchips.h>
  44. #include <linux/io.h>
  45. #include <linux/sched_clock.h>
  46. #include <asm/irq.h>
  47. #include <asm/mach/irq.h>
  48. #include <asm/mach/time.h>
  49. #include "hardware.h"
  50. #include "mux.h"
  51. #include "iomap.h"
  52. #include "common.h"
  53. #include "clock.h"
  54. #ifdef CONFIG_OMAP_MPU_TIMER
  55. #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
  56. #define OMAP_MPU_TIMER_OFFSET 0x100
  57. typedef struct {
  58. u32 cntl; /* CNTL_TIMER, R/W */
  59. u32 load_tim; /* LOAD_TIM, W */
  60. u32 read_tim; /* READ_TIM, R */
  61. } omap_mpu_timer_regs_t;
  62. #define omap_mpu_timer_base(n) \
  63. ((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
  64. (n)*OMAP_MPU_TIMER_OFFSET))
  65. static inline unsigned long notrace omap_mpu_timer_read(int nr)
  66. {
  67. omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
  68. return readl(&timer->read_tim);
  69. }
  70. static inline void omap_mpu_set_autoreset(int nr)
  71. {
  72. omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
  73. writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl);
  74. }
  75. static inline void omap_mpu_remove_autoreset(int nr)
  76. {
  77. omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
  78. writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl);
  79. }
  80. static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
  81. int autoreset)
  82. {
  83. omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
  84. unsigned int timerflags = MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST;
  85. if (autoreset)
  86. timerflags |= MPU_TIMER_AR;
  87. writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl);
  88. udelay(1);
  89. writel(load_val, &timer->load_tim);
  90. udelay(1);
  91. writel(timerflags, &timer->cntl);
  92. }
  93. static inline void omap_mpu_timer_stop(int nr)
  94. {
  95. omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
  96. writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl);
  97. }
  98. /*
  99. * ---------------------------------------------------------------------------
  100. * MPU timer 1 ... count down to zero, interrupt, reload
  101. * ---------------------------------------------------------------------------
  102. */
  103. static int omap_mpu_set_next_event(unsigned long cycles,
  104. struct clock_event_device *evt)
  105. {
  106. omap_mpu_timer_start(0, cycles, 0);
  107. return 0;
  108. }
  109. static int omap_mpu_set_oneshot(struct clock_event_device *evt)
  110. {
  111. omap_mpu_timer_stop(0);
  112. omap_mpu_remove_autoreset(0);
  113. return 0;
  114. }
  115. static int omap_mpu_set_periodic(struct clock_event_device *evt)
  116. {
  117. omap_mpu_set_autoreset(0);
  118. return 0;
  119. }
  120. static struct clock_event_device clockevent_mpu_timer1 = {
  121. .name = "mpu_timer1",
  122. .features = CLOCK_EVT_FEAT_PERIODIC |
  123. CLOCK_EVT_FEAT_ONESHOT,
  124. .set_next_event = omap_mpu_set_next_event,
  125. .set_state_periodic = omap_mpu_set_periodic,
  126. .set_state_oneshot = omap_mpu_set_oneshot,
  127. };
  128. static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
  129. {
  130. struct clock_event_device *evt = &clockevent_mpu_timer1;
  131. evt->event_handler(evt);
  132. return IRQ_HANDLED;
  133. }
  134. static __init void omap_init_mpu_timer(unsigned long rate)
  135. {
  136. if (request_irq(INT_TIMER1, omap_mpu_timer1_interrupt,
  137. IRQF_TIMER | IRQF_IRQPOLL, "mpu_timer1", NULL))
  138. pr_err("Failed to request irq %d (mpu_timer1)\n", INT_TIMER1);
  139. omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
  140. clockevent_mpu_timer1.cpumask = cpumask_of(0);
  141. clockevents_config_and_register(&clockevent_mpu_timer1, rate,
  142. 1, -1);
  143. }
  144. /*
  145. * ---------------------------------------------------------------------------
  146. * MPU timer 2 ... free running 32-bit clock source and scheduler clock
  147. * ---------------------------------------------------------------------------
  148. */
  149. static u64 notrace omap_mpu_read_sched_clock(void)
  150. {
  151. return ~omap_mpu_timer_read(1);
  152. }
  153. static void __init omap_init_clocksource(unsigned long rate)
  154. {
  155. omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(1);
  156. static char err[] __initdata = KERN_ERR
  157. "%s: can't register clocksource!\n";
  158. omap_mpu_timer_start(1, ~0, 1);
  159. sched_clock_register(omap_mpu_read_sched_clock, 32, rate);
  160. if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate,
  161. 300, 32, clocksource_mmio_readl_down))
  162. printk(err, "mpu_timer2");
  163. }
  164. static void __init omap_mpu_timer_init(void)
  165. {
  166. struct clk *ck_ref = clk_get(NULL, "ck_ref");
  167. unsigned long rate;
  168. BUG_ON(IS_ERR(ck_ref));
  169. rate = clk_get_rate(ck_ref);
  170. clk_put(ck_ref);
  171. /* PTV = 0 */
  172. rate /= 2;
  173. omap_init_mpu_timer(rate);
  174. omap_init_clocksource(rate);
  175. }
  176. #else
  177. static inline void omap_mpu_timer_init(void)
  178. {
  179. pr_err("Bogus timer, should not happen\n");
  180. }
  181. #endif /* CONFIG_OMAP_MPU_TIMER */
  182. /*
  183. * ---------------------------------------------------------------------------
  184. * Timer initialization
  185. * ---------------------------------------------------------------------------
  186. */
  187. void __init omap1_timer_init(void)
  188. {
  189. omap1_clk_init();
  190. omap1_mux_init();
  191. if (omap_32k_timer_init() != 0)
  192. omap_mpu_timer_init();
  193. }