sram.S 1.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * linux/arch/arm/plat-omap/sram-fn.S
  4. *
  5. * Functions that need to be run in internal SRAM
  6. */
  7. #include <linux/linkage.h>
  8. #include <linux/soc/ti/omap1-io.h>
  9. #include <asm/assembler.h>
  10. #include "hardware.h"
  11. #include "iomap.h"
  12. .text
  13. /*
  14. * Reprograms ULPD and CKCTL.
  15. */
  16. .align 3
  17. ENTRY(omap1_sram_reprogram_clock)
  18. stmfd sp!, {r0 - r12, lr} @ save registers on stack
  19. mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
  20. orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
  21. orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
  22. mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
  23. orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
  24. orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
  25. tst r0, #1 << 4 @ want lock mode?
  26. beq newck @ nope
  27. bic r0, r0, #1 << 4 @ else clear lock bit
  28. strh r0, [r2] @ set dpll into bypass mode
  29. orr r0, r0, #1 << 4 @ set lock bit again
  30. newck:
  31. strh r1, [r3] @ write new ckctl value
  32. strh r0, [r2] @ write new dpll value
  33. mov r4, #0x0700 @ let the clocks settle
  34. orr r4, r4, #0x00ff
  35. delay: sub r4, r4, #1
  36. cmp r4, #0
  37. bne delay
  38. lock: ldrh r4, [r2], #0 @ read back dpll value
  39. tst r0, #1 << 4 @ want lock mode?
  40. beq out @ nope
  41. tst r4, #1 << 0 @ dpll rate locked?
  42. beq lock @ try again
  43. out:
  44. ldmfd sp!, {r0 - r12, pc} @ restore regs and return
  45. ENTRY(omap1_sram_reprogram_clock_sz)
  46. .word . - omap1_sram_reprogram_clock