pm.h 8.7 KB

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  1. /*
  2. * arch/arm/mach-omap1/pm.h
  3. *
  4. * Header file for OMAP1 Power Management Routines
  5. *
  6. * Author: MontaVista Software, Inc.
  7. * [email protected]
  8. *
  9. * Copyright 2002 MontaVista Software Inc.
  10. *
  11. * Cleanup 2004 for Linux 2.6 by Dirk Behme <[email protected]>
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. *
  18. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  19. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  20. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  21. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  24. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  25. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28. *
  29. * You should have received a copy of the GNU General Public License along
  30. * with this program; if not, write to the Free Software Foundation, Inc.,
  31. * 675 Mass Ave, Cambridge, MA 02139, USA.
  32. */
  33. #ifndef __ARCH_ARM_MACH_OMAP1_PM_H
  34. #define __ARCH_ARM_MACH_OMAP1_PM_H
  35. #include <linux/soc/ti/omap1-io.h>
  36. /*
  37. * ----------------------------------------------------------------------------
  38. * Register and offset definitions to be used in PM assembler code
  39. * ----------------------------------------------------------------------------
  40. */
  41. #define CLKGEN_REG_ASM_BASE OMAP1_IO_ADDRESS(0xfffece00)
  42. #define ARM_IDLECT1_ASM_OFFSET 0x04
  43. #define ARM_IDLECT2_ASM_OFFSET 0x08
  44. #define TCMIF_ASM_BASE OMAP1_IO_ADDRESS(0xfffecc00)
  45. #define EMIFS_CONFIG_ASM_OFFSET 0x0c
  46. #define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
  47. /*
  48. * ----------------------------------------------------------------------------
  49. * Power management bitmasks
  50. * ----------------------------------------------------------------------------
  51. */
  52. #define IDLE_WAIT_CYCLES 0x00000fff
  53. #define PERIPHERAL_ENABLE 0x2
  54. #define SELF_REFRESH_MODE 0x0c000001
  55. #define IDLE_EMIFS_REQUEST 0xc
  56. #define MODEM_32K_EN 0x1
  57. #define PER_EN 0x1
  58. #define CPU_SUSPEND_SIZE 200
  59. #define ULPD_LOW_PWR_EN 0x0001
  60. #define ULPD_DEEP_SLEEP_TRANSITION_EN 0x0010
  61. #define ULPD_SETUP_ANALOG_CELL_3_VAL 0
  62. #define ULPD_POWER_CTRL_REG_VAL 0x0219
  63. #define DSP_IDLE_DELAY 10
  64. #define DSP_IDLE 0x0040
  65. #define DSP_RST 0x0004
  66. #define DSP_ENABLE 0x0002
  67. #define SUFFICIENT_DSP_RESET_TIME 1000
  68. #define DEFAULT_MPUI_CONFIG 0x05cf
  69. #define ENABLE_XORCLK 0x2
  70. #define DSP_CLOCK_ENABLE 0x2000
  71. #define DSP_IDLE_MODE 0x2
  72. #define TC_IDLE_REQUEST (0x0000000c)
  73. #define IRQ_LEVEL2 (1<<0)
  74. #define IRQ_KEYBOARD (1<<1)
  75. #define IRQ_UART2 (1<<15)
  76. #define PDE_BIT 0x08
  77. #define PWD_EN_BIT 0x04
  78. #define EN_PERCK_BIT 0x04
  79. #define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7
  80. #define OMAP1510_BIG_SLEEP_REQUEST 0x0cc5
  81. #define OMAP1510_IDLE_LOOP_REQUEST 0x0c00
  82. #define OMAP1510_IDLE_CLOCK_DOMAINS 0x2
  83. /* Both big sleep and deep sleep use same values. Difference is in ULPD. */
  84. #define OMAP1610_IDLECT1_SLEEP_VAL 0x13c7
  85. #define OMAP1610_IDLECT2_SLEEP_VAL 0x09c7
  86. #define OMAP1610_IDLECT3_VAL 0x3f
  87. #define OMAP1610_IDLECT3_SLEEP_ORMASK 0x2c
  88. #define OMAP1610_IDLECT3 0xfffece24
  89. #define OMAP1610_IDLE_LOOP_REQUEST 0x0400
  90. #define OMAP7XX_IDLECT1_SLEEP_VAL 0x16c7
  91. #define OMAP7XX_IDLECT2_SLEEP_VAL 0x09c7
  92. #define OMAP7XX_IDLECT3_VAL 0x3f
  93. #define OMAP7XX_IDLECT3 0xfffece24
  94. #define OMAP7XX_IDLE_LOOP_REQUEST 0x0C00
  95. #ifndef __ASSEMBLER__
  96. #include <linux/clk.h>
  97. extern struct kset power_subsys;
  98. extern void prevent_idle_sleep(void);
  99. extern void allow_idle_sleep(void);
  100. extern void omap1_pm_idle(void);
  101. extern void omap1_pm_suspend(void);
  102. extern void omap7xx_cpu_suspend(unsigned long, unsigned long);
  103. extern void omap1510_cpu_suspend(unsigned long, unsigned long);
  104. extern void omap1610_cpu_suspend(unsigned long, unsigned long);
  105. extern void omap7xx_idle_loop_suspend(void);
  106. extern void omap1510_idle_loop_suspend(void);
  107. extern void omap1610_idle_loop_suspend(void);
  108. extern unsigned int omap7xx_cpu_suspend_sz;
  109. extern unsigned int omap1510_cpu_suspend_sz;
  110. extern unsigned int omap1610_cpu_suspend_sz;
  111. extern unsigned int omap7xx_idle_loop_suspend_sz;
  112. extern unsigned int omap1510_idle_loop_suspend_sz;
  113. extern unsigned int omap1610_idle_loop_suspend_sz;
  114. #ifdef CONFIG_OMAP_SERIAL_WAKE
  115. extern void omap_serial_wake_trigger(int enable);
  116. #else
  117. #define omap_serial_wakeup_init() {}
  118. #define omap_serial_wake_trigger(x) {}
  119. #endif /* CONFIG_OMAP_SERIAL_WAKE */
  120. #define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
  121. #define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
  122. #define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
  123. #define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x)
  124. #define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
  125. #define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x]
  126. #define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
  127. #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
  128. #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
  129. #define MPUI7XX_SAVE(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] = omap_readl(x)
  130. #define MPUI7XX_RESTORE(x) omap_writel((mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]), (x))
  131. #define MPUI7XX_SHOW(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]
  132. #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
  133. #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
  134. #define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
  135. #define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
  136. #define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
  137. #define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
  138. /*
  139. * List of global OMAP registers to preserve.
  140. * More ones like CP and general purpose register values are preserved
  141. * with the stack pointer in sleep.S.
  142. */
  143. enum arm_save_state {
  144. ARM_SLEEP_SAVE_START = 0,
  145. /*
  146. * MPU control registers 32 bits
  147. */
  148. ARM_SLEEP_SAVE_ARM_CKCTL,
  149. ARM_SLEEP_SAVE_ARM_IDLECT1,
  150. ARM_SLEEP_SAVE_ARM_IDLECT2,
  151. ARM_SLEEP_SAVE_ARM_IDLECT3,
  152. ARM_SLEEP_SAVE_ARM_EWUPCT,
  153. ARM_SLEEP_SAVE_ARM_RSTCT1,
  154. ARM_SLEEP_SAVE_ARM_RSTCT2,
  155. ARM_SLEEP_SAVE_ARM_SYSST,
  156. ARM_SLEEP_SAVE_SIZE
  157. };
  158. enum dsp_save_state {
  159. DSP_SLEEP_SAVE_START = 0,
  160. /*
  161. * DSP registers 16 bits
  162. */
  163. DSP_SLEEP_SAVE_DSP_IDLECT2,
  164. DSP_SLEEP_SAVE_SIZE
  165. };
  166. enum ulpd_save_state {
  167. ULPD_SLEEP_SAVE_START = 0,
  168. /*
  169. * ULPD registers 16 bits
  170. */
  171. ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
  172. ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
  173. ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
  174. ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
  175. ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
  176. ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
  177. ULPD_SLEEP_SAVE_SIZE
  178. };
  179. enum mpui1510_save_state {
  180. MPUI1510_SLEEP_SAVE_START = 0,
  181. /*
  182. * MPUI registers 32 bits
  183. */
  184. MPUI1510_SLEEP_SAVE_MPUI_CTRL,
  185. MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
  186. MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
  187. MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
  188. MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
  189. MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
  190. MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
  191. MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
  192. #if defined(CONFIG_ARCH_OMAP15XX)
  193. MPUI1510_SLEEP_SAVE_SIZE
  194. #else
  195. MPUI1510_SLEEP_SAVE_SIZE = 0
  196. #endif
  197. };
  198. enum mpui7xx_save_state {
  199. MPUI7XX_SLEEP_SAVE_START = 0,
  200. /*
  201. * MPUI registers 32 bits
  202. */
  203. MPUI7XX_SLEEP_SAVE_MPUI_CTRL,
  204. MPUI7XX_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
  205. MPUI7XX_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
  206. MPUI7XX_SLEEP_SAVE_MPUI_DSP_STATUS,
  207. MPUI7XX_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
  208. MPUI7XX_SLEEP_SAVE_EMIFS_CONFIG,
  209. MPUI7XX_SLEEP_SAVE_OMAP_IH1_MIR,
  210. MPUI7XX_SLEEP_SAVE_OMAP_IH2_0_MIR,
  211. MPUI7XX_SLEEP_SAVE_OMAP_IH2_1_MIR,
  212. #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
  213. MPUI7XX_SLEEP_SAVE_SIZE
  214. #else
  215. MPUI7XX_SLEEP_SAVE_SIZE = 0
  216. #endif
  217. };
  218. enum mpui1610_save_state {
  219. MPUI1610_SLEEP_SAVE_START = 0,
  220. /*
  221. * MPUI registers 32 bits
  222. */
  223. MPUI1610_SLEEP_SAVE_MPUI_CTRL,
  224. MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
  225. MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
  226. MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
  227. MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
  228. MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
  229. MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
  230. MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
  231. MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
  232. MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
  233. MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
  234. #if defined(CONFIG_ARCH_OMAP16XX)
  235. MPUI1610_SLEEP_SAVE_SIZE
  236. #else
  237. MPUI1610_SLEEP_SAVE_SIZE = 0
  238. #endif
  239. };
  240. #endif /* ASSEMBLER */
  241. #endif /* __ASM_ARCH_OMAP_PM_H */