pm.c 19 KB

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  1. /*
  2. * linux/arch/arm/mach-omap1/pm.c
  3. *
  4. * OMAP Power Management Routines
  5. *
  6. * Original code for the SA11x0:
  7. * Copyright (c) 2001 Cliff Brake <[email protected]>
  8. *
  9. * Modified for the PXA250 by Nicolas Pitre:
  10. * Copyright (c) 2002 Monta Vista Software, Inc.
  11. *
  12. * Modified for the OMAP1510 by David Singleton:
  13. * Copyright (c) 2002 Monta Vista Software, Inc.
  14. *
  15. * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <[email protected]>
  16. *
  17. * This program is free software; you can redistribute it and/or modify it
  18. * under the terms of the GNU General Public License as published by the
  19. * Free Software Foundation; either version 2 of the License, or (at your
  20. * option) any later version.
  21. *
  22. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  23. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32. *
  33. * You should have received a copy of the GNU General Public License along
  34. * with this program; if not, write to the Free Software Foundation, Inc.,
  35. * 675 Mass Ave, Cambridge, MA 02139, USA.
  36. */
  37. #include <linux/suspend.h>
  38. #include <linux/sched.h>
  39. #include <linux/debugfs.h>
  40. #include <linux/seq_file.h>
  41. #include <linux/interrupt.h>
  42. #include <linux/sysfs.h>
  43. #include <linux/module.h>
  44. #include <linux/io.h>
  45. #include <linux/atomic.h>
  46. #include <linux/cpu.h>
  47. #include <asm/fncpy.h>
  48. #include <asm/system_misc.h>
  49. #include <asm/irq.h>
  50. #include <asm/mach/time.h>
  51. #include <asm/mach/irq.h>
  52. #include <linux/soc/ti/omap1-io.h>
  53. #include "tc.h"
  54. #include <linux/omap-dma.h>
  55. #include <clocksource/timer-ti-dm.h>
  56. #include "hardware.h"
  57. #include "mux.h"
  58. #include "irqs.h"
  59. #include "iomap.h"
  60. #include "clock.h"
  61. #include "pm.h"
  62. #include "soc.h"
  63. #include "sram.h"
  64. static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
  65. static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
  66. static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
  67. static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
  68. static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
  69. static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
  70. static unsigned short enable_dyn_sleep;
  71. static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
  72. char *buf)
  73. {
  74. return sprintf(buf, "%hu\n", enable_dyn_sleep);
  75. }
  76. static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
  77. const char * buf, size_t n)
  78. {
  79. unsigned short value;
  80. if (sscanf(buf, "%hu", &value) != 1 ||
  81. (value != 0 && value != 1) ||
  82. (value != 0 && !IS_ENABLED(CONFIG_OMAP_32K_TIMER))) {
  83. pr_err("idle_sleep_store: Invalid value\n");
  84. return -EINVAL;
  85. }
  86. enable_dyn_sleep = value;
  87. return n;
  88. }
  89. static struct kobj_attribute sleep_while_idle_attr =
  90. __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
  91. static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
  92. /*
  93. * Let's power down on idle, but only if we are really
  94. * idle, because once we start down the path of
  95. * going idle we continue to do idle even if we get
  96. * a clock tick interrupt . .
  97. */
  98. void omap1_pm_idle(void)
  99. {
  100. extern __u32 arm_idlect1_mask;
  101. __u32 use_idlect1 = arm_idlect1_mask;
  102. local_fiq_disable();
  103. #if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
  104. use_idlect1 = use_idlect1 & ~(1 << 9);
  105. #endif
  106. #ifdef CONFIG_OMAP_DM_TIMER
  107. use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
  108. #endif
  109. if (omap_dma_running())
  110. use_idlect1 &= ~(1 << 6);
  111. /*
  112. * We should be able to remove the do_sleep variable and multiple
  113. * tests above as soon as drivers, timer and DMA code have been fixed.
  114. * Even the sleep block count should become obsolete.
  115. */
  116. if ((use_idlect1 != ~0) || !enable_dyn_sleep) {
  117. __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
  118. if (cpu_is_omap15xx())
  119. use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
  120. else
  121. use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
  122. omap_writel(use_idlect1, ARM_IDLECT1);
  123. __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
  124. omap_writel(saved_idlect1, ARM_IDLECT1);
  125. local_fiq_enable();
  126. return;
  127. }
  128. omap_sram_suspend(omap_readl(ARM_IDLECT1),
  129. omap_readl(ARM_IDLECT2));
  130. local_fiq_enable();
  131. }
  132. /*
  133. * Configuration of the wakeup event is board specific. For the
  134. * moment we put it into this helper function. Later it may move
  135. * to board specific files.
  136. */
  137. static void omap_pm_wakeup_setup(void)
  138. {
  139. u32 level1_wake = 0;
  140. u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
  141. /*
  142. * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
  143. * and the L2 wakeup interrupts: keypad and UART2. Note that the
  144. * drivers must still separately call omap_set_gpio_wakeup() to
  145. * wake up to a GPIO interrupt.
  146. */
  147. if (cpu_is_omap7xx())
  148. level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
  149. OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
  150. else if (cpu_is_omap15xx())
  151. level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
  152. OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
  153. else if (cpu_is_omap16xx())
  154. level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
  155. OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
  156. omap_writel(~level1_wake, OMAP_IH1_MIR);
  157. if (cpu_is_omap7xx()) {
  158. omap_writel(~level2_wake, OMAP_IH2_0_MIR);
  159. omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
  160. OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
  161. OMAP_IH2_1_MIR);
  162. } else if (cpu_is_omap15xx()) {
  163. level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
  164. omap_writel(~level2_wake, OMAP_IH2_MIR);
  165. } else if (cpu_is_omap16xx()) {
  166. level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
  167. omap_writel(~level2_wake, OMAP_IH2_0_MIR);
  168. /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
  169. omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
  170. OMAP_IH2_1_MIR);
  171. omap_writel(~0x0, OMAP_IH2_2_MIR);
  172. omap_writel(~0x0, OMAP_IH2_3_MIR);
  173. }
  174. /* New IRQ agreement, recalculate in cascade order */
  175. omap_writel(1, OMAP_IH2_CONTROL);
  176. omap_writel(1, OMAP_IH1_CONTROL);
  177. }
  178. #define EN_DSPCK 13 /* ARM_CKCTL */
  179. #define EN_APICK 6 /* ARM_IDLECT2 */
  180. #define DSP_EN 1 /* ARM_RSTCT1 */
  181. void omap1_pm_suspend(void)
  182. {
  183. unsigned long arg0 = 0, arg1 = 0;
  184. printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n",
  185. omap_rev());
  186. omap_serial_wake_trigger(1);
  187. if (!cpu_is_omap15xx())
  188. omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
  189. /*
  190. * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
  191. */
  192. local_irq_disable();
  193. local_fiq_disable();
  194. /*
  195. * Step 2: save registers
  196. *
  197. * The omap is a strange/beautiful device. The caches, memory
  198. * and register state are preserved across power saves.
  199. * We have to save and restore very little register state to
  200. * idle the omap.
  201. *
  202. * Save interrupt, MPUI, ARM and UPLD control registers.
  203. */
  204. if (cpu_is_omap7xx()) {
  205. MPUI7XX_SAVE(OMAP_IH1_MIR);
  206. MPUI7XX_SAVE(OMAP_IH2_0_MIR);
  207. MPUI7XX_SAVE(OMAP_IH2_1_MIR);
  208. MPUI7XX_SAVE(MPUI_CTRL);
  209. MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
  210. MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
  211. MPUI7XX_SAVE(EMIFS_CONFIG);
  212. MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
  213. } else if (cpu_is_omap15xx()) {
  214. MPUI1510_SAVE(OMAP_IH1_MIR);
  215. MPUI1510_SAVE(OMAP_IH2_MIR);
  216. MPUI1510_SAVE(MPUI_CTRL);
  217. MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
  218. MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
  219. MPUI1510_SAVE(EMIFS_CONFIG);
  220. MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
  221. } else if (cpu_is_omap16xx()) {
  222. MPUI1610_SAVE(OMAP_IH1_MIR);
  223. MPUI1610_SAVE(OMAP_IH2_0_MIR);
  224. MPUI1610_SAVE(OMAP_IH2_1_MIR);
  225. MPUI1610_SAVE(OMAP_IH2_2_MIR);
  226. MPUI1610_SAVE(OMAP_IH2_3_MIR);
  227. MPUI1610_SAVE(MPUI_CTRL);
  228. MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
  229. MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
  230. MPUI1610_SAVE(EMIFS_CONFIG);
  231. MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
  232. }
  233. ARM_SAVE(ARM_CKCTL);
  234. ARM_SAVE(ARM_IDLECT1);
  235. ARM_SAVE(ARM_IDLECT2);
  236. if (!(cpu_is_omap15xx()))
  237. ARM_SAVE(ARM_IDLECT3);
  238. ARM_SAVE(ARM_EWUPCT);
  239. ARM_SAVE(ARM_RSTCT1);
  240. ARM_SAVE(ARM_RSTCT2);
  241. ARM_SAVE(ARM_SYSST);
  242. ULPD_SAVE(ULPD_CLOCK_CTRL);
  243. ULPD_SAVE(ULPD_STATUS_REQ);
  244. /* (Step 3 removed - we now allow deep sleep by default) */
  245. /*
  246. * Step 4: OMAP DSP Shutdown
  247. */
  248. /* stop DSP */
  249. omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
  250. /* shut down dsp_ck */
  251. if (!cpu_is_omap7xx())
  252. omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
  253. /* temporarily enabling api_ck to access DSP registers */
  254. omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
  255. /* save DSP registers */
  256. DSP_SAVE(DSP_IDLECT2);
  257. /* Stop all DSP domain clocks */
  258. __raw_writew(0, DSP_IDLECT2);
  259. /*
  260. * Step 5: Wakeup Event Setup
  261. */
  262. omap_pm_wakeup_setup();
  263. /*
  264. * Step 6: ARM and Traffic controller shutdown
  265. */
  266. /* disable ARM watchdog */
  267. omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
  268. omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
  269. /*
  270. * Step 6b: ARM and Traffic controller shutdown
  271. *
  272. * Step 6 continues here. Prepare jump to power management
  273. * assembly code in internal SRAM.
  274. *
  275. * Since the omap_cpu_suspend routine has been copied to
  276. * SRAM, we'll do an indirect procedure call to it and pass the
  277. * contents of arm_idlect1 and arm_idlect2 so it can restore
  278. * them when it wakes up and it will return.
  279. */
  280. arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
  281. arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
  282. /*
  283. * Step 6c: ARM and Traffic controller shutdown
  284. *
  285. * Jump to assembly code. The processor will stay there
  286. * until wake up.
  287. */
  288. omap_sram_suspend(arg0, arg1);
  289. /*
  290. * If we are here, processor is woken up!
  291. */
  292. /*
  293. * Restore DSP clocks
  294. */
  295. /* again temporarily enabling api_ck to access DSP registers */
  296. omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
  297. /* Restore DSP domain clocks */
  298. DSP_RESTORE(DSP_IDLECT2);
  299. /*
  300. * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
  301. */
  302. if (!(cpu_is_omap15xx()))
  303. ARM_RESTORE(ARM_IDLECT3);
  304. ARM_RESTORE(ARM_CKCTL);
  305. ARM_RESTORE(ARM_EWUPCT);
  306. ARM_RESTORE(ARM_RSTCT1);
  307. ARM_RESTORE(ARM_RSTCT2);
  308. ARM_RESTORE(ARM_SYSST);
  309. ULPD_RESTORE(ULPD_CLOCK_CTRL);
  310. ULPD_RESTORE(ULPD_STATUS_REQ);
  311. if (cpu_is_omap7xx()) {
  312. MPUI7XX_RESTORE(EMIFS_CONFIG);
  313. MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
  314. MPUI7XX_RESTORE(OMAP_IH1_MIR);
  315. MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
  316. MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
  317. } else if (cpu_is_omap15xx()) {
  318. MPUI1510_RESTORE(MPUI_CTRL);
  319. MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
  320. MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
  321. MPUI1510_RESTORE(EMIFS_CONFIG);
  322. MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
  323. MPUI1510_RESTORE(OMAP_IH1_MIR);
  324. MPUI1510_RESTORE(OMAP_IH2_MIR);
  325. } else if (cpu_is_omap16xx()) {
  326. MPUI1610_RESTORE(MPUI_CTRL);
  327. MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
  328. MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
  329. MPUI1610_RESTORE(EMIFS_CONFIG);
  330. MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
  331. MPUI1610_RESTORE(OMAP_IH1_MIR);
  332. MPUI1610_RESTORE(OMAP_IH2_0_MIR);
  333. MPUI1610_RESTORE(OMAP_IH2_1_MIR);
  334. MPUI1610_RESTORE(OMAP_IH2_2_MIR);
  335. MPUI1610_RESTORE(OMAP_IH2_3_MIR);
  336. }
  337. if (!cpu_is_omap15xx())
  338. omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
  339. /*
  340. * Re-enable interrupts
  341. */
  342. local_irq_enable();
  343. local_fiq_enable();
  344. omap_serial_wake_trigger(0);
  345. printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
  346. omap_rev());
  347. }
  348. #ifdef CONFIG_DEBUG_FS
  349. /*
  350. * Read system PM registers for debugging
  351. */
  352. static int omap_pm_debug_show(struct seq_file *m, void *v)
  353. {
  354. ARM_SAVE(ARM_CKCTL);
  355. ARM_SAVE(ARM_IDLECT1);
  356. ARM_SAVE(ARM_IDLECT2);
  357. if (!(cpu_is_omap15xx()))
  358. ARM_SAVE(ARM_IDLECT3);
  359. ARM_SAVE(ARM_EWUPCT);
  360. ARM_SAVE(ARM_RSTCT1);
  361. ARM_SAVE(ARM_RSTCT2);
  362. ARM_SAVE(ARM_SYSST);
  363. ULPD_SAVE(ULPD_IT_STATUS);
  364. ULPD_SAVE(ULPD_CLOCK_CTRL);
  365. ULPD_SAVE(ULPD_SOFT_REQ);
  366. ULPD_SAVE(ULPD_STATUS_REQ);
  367. ULPD_SAVE(ULPD_DPLL_CTRL);
  368. ULPD_SAVE(ULPD_POWER_CTRL);
  369. if (cpu_is_omap7xx()) {
  370. MPUI7XX_SAVE(MPUI_CTRL);
  371. MPUI7XX_SAVE(MPUI_DSP_STATUS);
  372. MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
  373. MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
  374. MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
  375. MPUI7XX_SAVE(EMIFS_CONFIG);
  376. } else if (cpu_is_omap15xx()) {
  377. MPUI1510_SAVE(MPUI_CTRL);
  378. MPUI1510_SAVE(MPUI_DSP_STATUS);
  379. MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
  380. MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
  381. MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
  382. MPUI1510_SAVE(EMIFS_CONFIG);
  383. } else if (cpu_is_omap16xx()) {
  384. MPUI1610_SAVE(MPUI_CTRL);
  385. MPUI1610_SAVE(MPUI_DSP_STATUS);
  386. MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
  387. MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
  388. MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
  389. MPUI1610_SAVE(EMIFS_CONFIG);
  390. }
  391. seq_printf(m,
  392. "ARM_CKCTL_REG: 0x%-8x \n"
  393. "ARM_IDLECT1_REG: 0x%-8x \n"
  394. "ARM_IDLECT2_REG: 0x%-8x \n"
  395. "ARM_IDLECT3_REG: 0x%-8x \n"
  396. "ARM_EWUPCT_REG: 0x%-8x \n"
  397. "ARM_RSTCT1_REG: 0x%-8x \n"
  398. "ARM_RSTCT2_REG: 0x%-8x \n"
  399. "ARM_SYSST_REG: 0x%-8x \n"
  400. "ULPD_IT_STATUS_REG: 0x%-4x \n"
  401. "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
  402. "ULPD_SOFT_REQ_REG: 0x%-4x \n"
  403. "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
  404. "ULPD_STATUS_REQ_REG: 0x%-4x \n"
  405. "ULPD_POWER_CTRL_REG: 0x%-4x \n",
  406. ARM_SHOW(ARM_CKCTL),
  407. ARM_SHOW(ARM_IDLECT1),
  408. ARM_SHOW(ARM_IDLECT2),
  409. ARM_SHOW(ARM_IDLECT3),
  410. ARM_SHOW(ARM_EWUPCT),
  411. ARM_SHOW(ARM_RSTCT1),
  412. ARM_SHOW(ARM_RSTCT2),
  413. ARM_SHOW(ARM_SYSST),
  414. ULPD_SHOW(ULPD_IT_STATUS),
  415. ULPD_SHOW(ULPD_CLOCK_CTRL),
  416. ULPD_SHOW(ULPD_SOFT_REQ),
  417. ULPD_SHOW(ULPD_DPLL_CTRL),
  418. ULPD_SHOW(ULPD_STATUS_REQ),
  419. ULPD_SHOW(ULPD_POWER_CTRL));
  420. if (cpu_is_omap7xx()) {
  421. seq_printf(m,
  422. "MPUI7XX_CTRL_REG 0x%-8x \n"
  423. "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n"
  424. "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
  425. "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n"
  426. "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n"
  427. "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n",
  428. MPUI7XX_SHOW(MPUI_CTRL),
  429. MPUI7XX_SHOW(MPUI_DSP_STATUS),
  430. MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
  431. MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
  432. MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
  433. MPUI7XX_SHOW(EMIFS_CONFIG));
  434. } else if (cpu_is_omap15xx()) {
  435. seq_printf(m,
  436. "MPUI1510_CTRL_REG 0x%-8x \n"
  437. "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
  438. "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
  439. "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
  440. "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
  441. "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
  442. MPUI1510_SHOW(MPUI_CTRL),
  443. MPUI1510_SHOW(MPUI_DSP_STATUS),
  444. MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
  445. MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
  446. MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
  447. MPUI1510_SHOW(EMIFS_CONFIG));
  448. } else if (cpu_is_omap16xx()) {
  449. seq_printf(m,
  450. "MPUI1610_CTRL_REG 0x%-8x \n"
  451. "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
  452. "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
  453. "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
  454. "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
  455. "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
  456. MPUI1610_SHOW(MPUI_CTRL),
  457. MPUI1610_SHOW(MPUI_DSP_STATUS),
  458. MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
  459. MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
  460. MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
  461. MPUI1610_SHOW(EMIFS_CONFIG));
  462. }
  463. return 0;
  464. }
  465. DEFINE_SHOW_ATTRIBUTE(omap_pm_debug);
  466. static void omap_pm_init_debugfs(void)
  467. {
  468. struct dentry *d;
  469. d = debugfs_create_dir("pm_debug", NULL);
  470. debugfs_create_file("omap_pm", S_IWUSR | S_IRUGO, d, NULL,
  471. &omap_pm_debug_fops);
  472. }
  473. #endif /* CONFIG_DEBUG_FS */
  474. /*
  475. * omap_pm_prepare - Do preliminary suspend work.
  476. *
  477. */
  478. static int omap_pm_prepare(void)
  479. {
  480. /* We cannot sleep in idle until we have resumed */
  481. cpu_idle_poll_ctrl(true);
  482. return 0;
  483. }
  484. /*
  485. * omap_pm_enter - Actually enter a sleep state.
  486. * @state: State we're entering.
  487. *
  488. */
  489. static int omap_pm_enter(suspend_state_t state)
  490. {
  491. switch (state)
  492. {
  493. case PM_SUSPEND_MEM:
  494. omap1_pm_suspend();
  495. break;
  496. default:
  497. return -EINVAL;
  498. }
  499. return 0;
  500. }
  501. /**
  502. * omap_pm_finish - Finish up suspend sequence.
  503. *
  504. * This is called after we wake back up (or if entering the sleep state
  505. * failed).
  506. */
  507. static void omap_pm_finish(void)
  508. {
  509. cpu_idle_poll_ctrl(false);
  510. }
  511. static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
  512. {
  513. return IRQ_HANDLED;
  514. }
  515. static const struct platform_suspend_ops omap_pm_ops = {
  516. .prepare = omap_pm_prepare,
  517. .enter = omap_pm_enter,
  518. .finish = omap_pm_finish,
  519. .valid = suspend_valid_only_mem,
  520. };
  521. static int __init omap_pm_init(void)
  522. {
  523. int error = 0;
  524. int irq;
  525. if (!cpu_class_is_omap1())
  526. return -ENODEV;
  527. pr_info("Power Management for TI OMAP.\n");
  528. if (!IS_ENABLED(CONFIG_OMAP_32K_TIMER))
  529. pr_info("OMAP1 PM: sleep states in idle disabled due to no 32KiHz timer\n");
  530. if (!IS_ENABLED(CONFIG_OMAP_DM_TIMER))
  531. pr_info("OMAP1 PM: sleep states in idle disabled due to no DMTIMER support\n");
  532. if (IS_ENABLED(CONFIG_OMAP_32K_TIMER) &&
  533. IS_ENABLED(CONFIG_OMAP_DM_TIMER)) {
  534. /* OMAP16xx only */
  535. pr_info("OMAP1 PM: sleep states in idle enabled\n");
  536. enable_dyn_sleep = 1;
  537. }
  538. /*
  539. * We copy the assembler sleep/wakeup routines to SRAM.
  540. * These routines need to be in SRAM as that's the only
  541. * memory the MPU can see when it wakes up.
  542. */
  543. if (cpu_is_omap7xx()) {
  544. omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
  545. omap7xx_cpu_suspend_sz);
  546. } else if (cpu_is_omap15xx()) {
  547. omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
  548. omap1510_cpu_suspend_sz);
  549. } else if (cpu_is_omap16xx()) {
  550. omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
  551. omap1610_cpu_suspend_sz);
  552. }
  553. if (omap_sram_suspend == NULL) {
  554. printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
  555. return -ENODEV;
  556. }
  557. arm_pm_idle = omap1_pm_idle;
  558. if (cpu_is_omap7xx())
  559. irq = INT_7XX_WAKE_UP_REQ;
  560. else if (cpu_is_omap16xx())
  561. irq = INT_1610_WAKE_UP_REQ;
  562. else
  563. irq = -1;
  564. if (irq >= 0) {
  565. if (request_irq(irq, omap_wakeup_interrupt, 0, "peripheral wakeup", NULL))
  566. pr_err("Failed to request irq %d (peripheral wakeup)\n", irq);
  567. }
  568. /* Program new power ramp-up time
  569. * (0 for most boards since we don't lower voltage when in deep sleep)
  570. */
  571. omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
  572. /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
  573. omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
  574. /* Configure IDLECT3 */
  575. if (cpu_is_omap7xx())
  576. omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
  577. else if (cpu_is_omap16xx())
  578. omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
  579. suspend_set_ops(&omap_pm_ops);
  580. #ifdef CONFIG_DEBUG_FS
  581. omap_pm_init_debugfs();
  582. #endif
  583. error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
  584. if (error)
  585. printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
  586. if (cpu_is_omap16xx()) {
  587. /* configure LOW_PWR pin */
  588. omap_cfg_reg(T20_1610_LOW_PWR);
  589. }
  590. return error;
  591. }
  592. __initcall(omap_pm_init);