mcbsp.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/mach-omap1/mcbsp.c
  4. *
  5. * Copyright (C) 2008 Instituto Nokia de Tecnologia
  6. * Contact: Eduardo Valentin <[email protected]>
  7. *
  8. * Multichannel mode not supported.
  9. */
  10. #include <linux/ioport.h>
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/clk.h>
  14. #include <linux/err.h>
  15. #include <linux/io.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/omap-dma.h>
  19. #include <linux/soc/ti/omap1-io.h>
  20. #include <linux/platform_data/asoc-ti-mcbsp.h>
  21. #include "mux.h"
  22. #include "soc.h"
  23. #include "irqs.h"
  24. #include "iomap.h"
  25. #define DPS_RSTCT2_PER_EN (1 << 0)
  26. #define DSP_RSTCT2_WD_PER_EN (1 << 1)
  27. static int dsp_use;
  28. static struct clk *api_clk;
  29. static struct clk *dsp_clk;
  30. static struct platform_device **omap_mcbsp_devices;
  31. static void omap1_mcbsp_request(unsigned int id)
  32. {
  33. /*
  34. * On 1510, 1610 and 1710, McBSP1 and McBSP3
  35. * are DSP public peripherals.
  36. */
  37. if (id == 0 || id == 2) {
  38. if (dsp_use++ == 0) {
  39. api_clk = clk_get(NULL, "api_ck");
  40. dsp_clk = clk_get(NULL, "dsp_ck");
  41. if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) {
  42. clk_prepare_enable(api_clk);
  43. clk_prepare_enable(dsp_clk);
  44. /*
  45. * DSP external peripheral reset
  46. * FIXME: This should be moved to dsp code
  47. */
  48. __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
  49. DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
  50. }
  51. }
  52. }
  53. }
  54. static void omap1_mcbsp_free(unsigned int id)
  55. {
  56. if (id == 0 || id == 2) {
  57. if (--dsp_use == 0) {
  58. if (!IS_ERR(api_clk)) {
  59. clk_disable_unprepare(api_clk);
  60. clk_put(api_clk);
  61. }
  62. if (!IS_ERR(dsp_clk)) {
  63. clk_disable_unprepare(dsp_clk);
  64. clk_put(dsp_clk);
  65. }
  66. }
  67. }
  68. }
  69. static struct omap_mcbsp_ops omap1_mcbsp_ops = {
  70. .request = omap1_mcbsp_request,
  71. .free = omap1_mcbsp_free,
  72. };
  73. #define OMAP7XX_MCBSP1_BASE 0xfffb1000
  74. #define OMAP7XX_MCBSP2_BASE 0xfffb1800
  75. #define OMAP1510_MCBSP1_BASE 0xe1011800
  76. #define OMAP1510_MCBSP2_BASE 0xfffb1000
  77. #define OMAP1510_MCBSP3_BASE 0xe1017000
  78. #define OMAP1610_MCBSP1_BASE 0xe1011800
  79. #define OMAP1610_MCBSP2_BASE 0xfffb1000
  80. #define OMAP1610_MCBSP3_BASE 0xe1017000
  81. struct resource omap7xx_mcbsp_res[][6] = {
  82. {
  83. {
  84. .start = OMAP7XX_MCBSP1_BASE,
  85. .end = OMAP7XX_MCBSP1_BASE + SZ_256,
  86. .flags = IORESOURCE_MEM,
  87. },
  88. {
  89. .name = "rx",
  90. .start = INT_7XX_McBSP1RX,
  91. .flags = IORESOURCE_IRQ,
  92. },
  93. {
  94. .name = "tx",
  95. .start = INT_7XX_McBSP1TX,
  96. .flags = IORESOURCE_IRQ,
  97. },
  98. {
  99. .name = "rx",
  100. .start = 9,
  101. .flags = IORESOURCE_DMA,
  102. },
  103. {
  104. .name = "tx",
  105. .start = 8,
  106. .flags = IORESOURCE_DMA,
  107. },
  108. },
  109. {
  110. {
  111. .start = OMAP7XX_MCBSP2_BASE,
  112. .end = OMAP7XX_MCBSP2_BASE + SZ_256,
  113. .flags = IORESOURCE_MEM,
  114. },
  115. {
  116. .name = "rx",
  117. .start = INT_7XX_McBSP2RX,
  118. .flags = IORESOURCE_IRQ,
  119. },
  120. {
  121. .name = "tx",
  122. .start = INT_7XX_McBSP2TX,
  123. .flags = IORESOURCE_IRQ,
  124. },
  125. {
  126. .name = "rx",
  127. .start = 11,
  128. .flags = IORESOURCE_DMA,
  129. },
  130. {
  131. .name = "tx",
  132. .start = 10,
  133. .flags = IORESOURCE_DMA,
  134. },
  135. },
  136. };
  137. #define omap7xx_mcbsp_res_0 omap7xx_mcbsp_res[0]
  138. static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
  139. {
  140. .ops = &omap1_mcbsp_ops,
  141. },
  142. {
  143. .ops = &omap1_mcbsp_ops,
  144. },
  145. };
  146. #define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1])
  147. #define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res)
  148. struct resource omap15xx_mcbsp_res[][6] = {
  149. {
  150. {
  151. .start = OMAP1510_MCBSP1_BASE,
  152. .end = OMAP1510_MCBSP1_BASE + SZ_256,
  153. .flags = IORESOURCE_MEM,
  154. },
  155. {
  156. .name = "rx",
  157. .start = INT_McBSP1RX,
  158. .flags = IORESOURCE_IRQ,
  159. },
  160. {
  161. .name = "tx",
  162. .start = INT_McBSP1TX,
  163. .flags = IORESOURCE_IRQ,
  164. },
  165. {
  166. .name = "rx",
  167. .start = 9,
  168. .flags = IORESOURCE_DMA,
  169. },
  170. {
  171. .name = "tx",
  172. .start = 8,
  173. .flags = IORESOURCE_DMA,
  174. },
  175. },
  176. {
  177. {
  178. .start = OMAP1510_MCBSP2_BASE,
  179. .end = OMAP1510_MCBSP2_BASE + SZ_256,
  180. .flags = IORESOURCE_MEM,
  181. },
  182. {
  183. .name = "rx",
  184. .start = INT_1510_SPI_RX,
  185. .flags = IORESOURCE_IRQ,
  186. },
  187. {
  188. .name = "tx",
  189. .start = INT_1510_SPI_TX,
  190. .flags = IORESOURCE_IRQ,
  191. },
  192. {
  193. .name = "rx",
  194. .start = 17,
  195. .flags = IORESOURCE_DMA,
  196. },
  197. {
  198. .name = "tx",
  199. .start = 16,
  200. .flags = IORESOURCE_DMA,
  201. },
  202. },
  203. {
  204. {
  205. .start = OMAP1510_MCBSP3_BASE,
  206. .end = OMAP1510_MCBSP3_BASE + SZ_256,
  207. .flags = IORESOURCE_MEM,
  208. },
  209. {
  210. .name = "rx",
  211. .start = INT_McBSP3RX,
  212. .flags = IORESOURCE_IRQ,
  213. },
  214. {
  215. .name = "tx",
  216. .start = INT_McBSP3TX,
  217. .flags = IORESOURCE_IRQ,
  218. },
  219. {
  220. .name = "rx",
  221. .start = 11,
  222. .flags = IORESOURCE_DMA,
  223. },
  224. {
  225. .name = "tx",
  226. .start = 10,
  227. .flags = IORESOURCE_DMA,
  228. },
  229. },
  230. };
  231. #define omap15xx_mcbsp_res_0 omap15xx_mcbsp_res[0]
  232. static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
  233. {
  234. .ops = &omap1_mcbsp_ops,
  235. },
  236. {
  237. .ops = &omap1_mcbsp_ops,
  238. },
  239. {
  240. .ops = &omap1_mcbsp_ops,
  241. },
  242. };
  243. #define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1])
  244. #define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res)
  245. struct resource omap16xx_mcbsp_res[][6] = {
  246. {
  247. {
  248. .start = OMAP1610_MCBSP1_BASE,
  249. .end = OMAP1610_MCBSP1_BASE + SZ_256,
  250. .flags = IORESOURCE_MEM,
  251. },
  252. {
  253. .name = "rx",
  254. .start = INT_McBSP1RX,
  255. .flags = IORESOURCE_IRQ,
  256. },
  257. {
  258. .name = "tx",
  259. .start = INT_McBSP1TX,
  260. .flags = IORESOURCE_IRQ,
  261. },
  262. {
  263. .name = "rx",
  264. .start = 9,
  265. .flags = IORESOURCE_DMA,
  266. },
  267. {
  268. .name = "tx",
  269. .start = 8,
  270. .flags = IORESOURCE_DMA,
  271. },
  272. },
  273. {
  274. {
  275. .start = OMAP1610_MCBSP2_BASE,
  276. .end = OMAP1610_MCBSP2_BASE + SZ_256,
  277. .flags = IORESOURCE_MEM,
  278. },
  279. {
  280. .name = "rx",
  281. .start = INT_1610_McBSP2_RX,
  282. .flags = IORESOURCE_IRQ,
  283. },
  284. {
  285. .name = "tx",
  286. .start = INT_1610_McBSP2_TX,
  287. .flags = IORESOURCE_IRQ,
  288. },
  289. {
  290. .name = "rx",
  291. .start = 17,
  292. .flags = IORESOURCE_DMA,
  293. },
  294. {
  295. .name = "tx",
  296. .start = 16,
  297. .flags = IORESOURCE_DMA,
  298. },
  299. },
  300. {
  301. {
  302. .start = OMAP1610_MCBSP3_BASE,
  303. .end = OMAP1610_MCBSP3_BASE + SZ_256,
  304. .flags = IORESOURCE_MEM,
  305. },
  306. {
  307. .name = "rx",
  308. .start = INT_McBSP3RX,
  309. .flags = IORESOURCE_IRQ,
  310. },
  311. {
  312. .name = "tx",
  313. .start = INT_McBSP3TX,
  314. .flags = IORESOURCE_IRQ,
  315. },
  316. {
  317. .name = "rx",
  318. .start = 11,
  319. .flags = IORESOURCE_DMA,
  320. },
  321. {
  322. .name = "tx",
  323. .start = 10,
  324. .flags = IORESOURCE_DMA,
  325. },
  326. },
  327. };
  328. #define omap16xx_mcbsp_res_0 omap16xx_mcbsp_res[0]
  329. static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
  330. {
  331. .ops = &omap1_mcbsp_ops,
  332. },
  333. {
  334. .ops = &omap1_mcbsp_ops,
  335. },
  336. {
  337. .ops = &omap1_mcbsp_ops,
  338. },
  339. };
  340. #define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1])
  341. #define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res)
  342. static void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
  343. struct omap_mcbsp_platform_data *config, int size)
  344. {
  345. int i;
  346. omap_mcbsp_devices = kcalloc(size, sizeof(struct platform_device *),
  347. GFP_KERNEL);
  348. if (!omap_mcbsp_devices) {
  349. printk(KERN_ERR "Could not register McBSP devices\n");
  350. return;
  351. }
  352. for (i = 0; i < size; i++) {
  353. struct platform_device *new_mcbsp;
  354. int ret;
  355. new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
  356. if (!new_mcbsp)
  357. continue;
  358. platform_device_add_resources(new_mcbsp, &res[i * res_count],
  359. res_count);
  360. config[i].reg_size = 2;
  361. config[i].reg_step = 2;
  362. new_mcbsp->dev.platform_data = &config[i];
  363. ret = platform_device_add(new_mcbsp);
  364. if (ret) {
  365. platform_device_put(new_mcbsp);
  366. continue;
  367. }
  368. omap_mcbsp_devices[i] = new_mcbsp;
  369. }
  370. }
  371. static int __init omap1_mcbsp_init(void)
  372. {
  373. if (!cpu_class_is_omap1())
  374. return -ENODEV;
  375. if (cpu_is_omap7xx())
  376. omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0,
  377. OMAP7XX_MCBSP_RES_SZ,
  378. omap7xx_mcbsp_pdata,
  379. OMAP7XX_MCBSP_COUNT);
  380. if (cpu_is_omap15xx())
  381. omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res_0,
  382. OMAP15XX_MCBSP_RES_SZ,
  383. omap15xx_mcbsp_pdata,
  384. OMAP15XX_MCBSP_COUNT);
  385. if (cpu_is_omap16xx())
  386. omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res_0,
  387. OMAP16XX_MCBSP_RES_SZ,
  388. omap16xx_mcbsp_pdata,
  389. OMAP16XX_MCBSP_COUNT);
  390. return 0;
  391. }
  392. arch_initcall(omap1_mcbsp_init);