gpio7xx.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * OMAP7xx specific gpio init
  4. *
  5. * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
  6. *
  7. * Author:
  8. * Charulatha V <[email protected]>
  9. */
  10. #include <linux/gpio.h>
  11. #include <linux/platform_data/gpio-omap.h>
  12. #include "irqs.h"
  13. #include "soc.h"
  14. #define OMAP7XX_GPIO1_BASE 0xfffbc000
  15. #define OMAP7XX_GPIO2_BASE 0xfffbc800
  16. #define OMAP7XX_GPIO3_BASE 0xfffbd000
  17. #define OMAP7XX_GPIO4_BASE 0xfffbd800
  18. #define OMAP7XX_GPIO5_BASE 0xfffbe000
  19. #define OMAP7XX_GPIO6_BASE 0xfffbe800
  20. #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
  21. /* mpu gpio */
  22. static struct resource omap7xx_mpu_gpio_resources[] = {
  23. {
  24. .start = OMAP1_MPUIO_VBASE,
  25. .end = OMAP1_MPUIO_VBASE + SZ_2K - 1,
  26. .flags = IORESOURCE_MEM,
  27. },
  28. {
  29. .start = INT_7XX_MPUIO,
  30. .flags = IORESOURCE_IRQ,
  31. },
  32. };
  33. static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
  34. .revision = USHRT_MAX,
  35. .direction = OMAP_MPUIO_IO_CNTL / 2,
  36. .datain = OMAP_MPUIO_INPUT_LATCH / 2,
  37. .dataout = OMAP_MPUIO_OUTPUT / 2,
  38. .irqstatus = OMAP_MPUIO_GPIO_INT / 2,
  39. .irqenable = OMAP_MPUIO_GPIO_MASKIT / 2,
  40. .irqenable_inv = true,
  41. .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE >> 1,
  42. };
  43. static struct omap_gpio_platform_data omap7xx_mpu_gpio_config = {
  44. .is_mpuio = true,
  45. .bank_width = 16,
  46. .bank_stride = 2,
  47. .regs = &omap7xx_mpuio_regs,
  48. };
  49. static struct platform_device omap7xx_mpu_gpio = {
  50. .name = "omap_gpio",
  51. .id = 0,
  52. .dev = {
  53. .platform_data = &omap7xx_mpu_gpio_config,
  54. },
  55. .num_resources = ARRAY_SIZE(omap7xx_mpu_gpio_resources),
  56. .resource = omap7xx_mpu_gpio_resources,
  57. };
  58. /* gpio1 */
  59. static struct resource omap7xx_gpio1_resources[] = {
  60. {
  61. .start = OMAP7XX_GPIO1_BASE,
  62. .end = OMAP7XX_GPIO1_BASE + SZ_2K - 1,
  63. .flags = IORESOURCE_MEM,
  64. },
  65. {
  66. .start = INT_7XX_GPIO_BANK1,
  67. .flags = IORESOURCE_IRQ,
  68. },
  69. };
  70. static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
  71. .revision = USHRT_MAX,
  72. .direction = OMAP7XX_GPIO_DIR_CONTROL,
  73. .datain = OMAP7XX_GPIO_DATA_INPUT,
  74. .dataout = OMAP7XX_GPIO_DATA_OUTPUT,
  75. .irqstatus = OMAP7XX_GPIO_INT_STATUS,
  76. .irqenable = OMAP7XX_GPIO_INT_MASK,
  77. .irqenable_inv = true,
  78. .irqctrl = OMAP7XX_GPIO_INT_CONTROL,
  79. };
  80. static struct omap_gpio_platform_data omap7xx_gpio1_config = {
  81. .bank_width = 32,
  82. .regs = &omap7xx_gpio_regs,
  83. };
  84. static struct platform_device omap7xx_gpio1 = {
  85. .name = "omap_gpio",
  86. .id = 1,
  87. .dev = {
  88. .platform_data = &omap7xx_gpio1_config,
  89. },
  90. .num_resources = ARRAY_SIZE(omap7xx_gpio1_resources),
  91. .resource = omap7xx_gpio1_resources,
  92. };
  93. /* gpio2 */
  94. static struct resource omap7xx_gpio2_resources[] = {
  95. {
  96. .start = OMAP7XX_GPIO2_BASE,
  97. .end = OMAP7XX_GPIO2_BASE + SZ_2K - 1,
  98. .flags = IORESOURCE_MEM,
  99. },
  100. {
  101. .start = INT_7XX_GPIO_BANK2,
  102. .flags = IORESOURCE_IRQ,
  103. },
  104. };
  105. static struct omap_gpio_platform_data omap7xx_gpio2_config = {
  106. .bank_width = 32,
  107. .regs = &omap7xx_gpio_regs,
  108. };
  109. static struct platform_device omap7xx_gpio2 = {
  110. .name = "omap_gpio",
  111. .id = 2,
  112. .dev = {
  113. .platform_data = &omap7xx_gpio2_config,
  114. },
  115. .num_resources = ARRAY_SIZE(omap7xx_gpio2_resources),
  116. .resource = omap7xx_gpio2_resources,
  117. };
  118. /* gpio3 */
  119. static struct resource omap7xx_gpio3_resources[] = {
  120. {
  121. .start = OMAP7XX_GPIO3_BASE,
  122. .end = OMAP7XX_GPIO3_BASE + SZ_2K - 1,
  123. .flags = IORESOURCE_MEM,
  124. },
  125. {
  126. .start = INT_7XX_GPIO_BANK3,
  127. .flags = IORESOURCE_IRQ,
  128. },
  129. };
  130. static struct omap_gpio_platform_data omap7xx_gpio3_config = {
  131. .bank_width = 32,
  132. .regs = &omap7xx_gpio_regs,
  133. };
  134. static struct platform_device omap7xx_gpio3 = {
  135. .name = "omap_gpio",
  136. .id = 3,
  137. .dev = {
  138. .platform_data = &omap7xx_gpio3_config,
  139. },
  140. .num_resources = ARRAY_SIZE(omap7xx_gpio3_resources),
  141. .resource = omap7xx_gpio3_resources,
  142. };
  143. /* gpio4 */
  144. static struct resource omap7xx_gpio4_resources[] = {
  145. {
  146. .start = OMAP7XX_GPIO4_BASE,
  147. .end = OMAP7XX_GPIO4_BASE + SZ_2K - 1,
  148. .flags = IORESOURCE_MEM,
  149. },
  150. {
  151. .start = INT_7XX_GPIO_BANK4,
  152. .flags = IORESOURCE_IRQ,
  153. },
  154. };
  155. static struct omap_gpio_platform_data omap7xx_gpio4_config = {
  156. .bank_width = 32,
  157. .regs = &omap7xx_gpio_regs,
  158. };
  159. static struct platform_device omap7xx_gpio4 = {
  160. .name = "omap_gpio",
  161. .id = 4,
  162. .dev = {
  163. .platform_data = &omap7xx_gpio4_config,
  164. },
  165. .num_resources = ARRAY_SIZE(omap7xx_gpio4_resources),
  166. .resource = omap7xx_gpio4_resources,
  167. };
  168. /* gpio5 */
  169. static struct resource omap7xx_gpio5_resources[] = {
  170. {
  171. .start = OMAP7XX_GPIO5_BASE,
  172. .end = OMAP7XX_GPIO5_BASE + SZ_2K - 1,
  173. .flags = IORESOURCE_MEM,
  174. },
  175. {
  176. .start = INT_7XX_GPIO_BANK5,
  177. .flags = IORESOURCE_IRQ,
  178. },
  179. };
  180. static struct omap_gpio_platform_data omap7xx_gpio5_config = {
  181. .bank_width = 32,
  182. .regs = &omap7xx_gpio_regs,
  183. };
  184. static struct platform_device omap7xx_gpio5 = {
  185. .name = "omap_gpio",
  186. .id = 5,
  187. .dev = {
  188. .platform_data = &omap7xx_gpio5_config,
  189. },
  190. .num_resources = ARRAY_SIZE(omap7xx_gpio5_resources),
  191. .resource = omap7xx_gpio5_resources,
  192. };
  193. /* gpio6 */
  194. static struct resource omap7xx_gpio6_resources[] = {
  195. {
  196. .start = OMAP7XX_GPIO6_BASE,
  197. .end = OMAP7XX_GPIO6_BASE + SZ_2K - 1,
  198. .flags = IORESOURCE_MEM,
  199. },
  200. {
  201. .start = INT_7XX_GPIO_BANK6,
  202. .flags = IORESOURCE_IRQ,
  203. },
  204. };
  205. static struct omap_gpio_platform_data omap7xx_gpio6_config = {
  206. .bank_width = 32,
  207. .regs = &omap7xx_gpio_regs,
  208. };
  209. static struct platform_device omap7xx_gpio6 = {
  210. .name = "omap_gpio",
  211. .id = 6,
  212. .dev = {
  213. .platform_data = &omap7xx_gpio6_config,
  214. },
  215. .num_resources = ARRAY_SIZE(omap7xx_gpio6_resources),
  216. .resource = omap7xx_gpio6_resources,
  217. };
  218. static struct platform_device *omap7xx_gpio_dev[] __initdata = {
  219. &omap7xx_mpu_gpio,
  220. &omap7xx_gpio1,
  221. &omap7xx_gpio2,
  222. &omap7xx_gpio3,
  223. &omap7xx_gpio4,
  224. &omap7xx_gpio5,
  225. &omap7xx_gpio6,
  226. };
  227. /*
  228. * omap7xx_gpio_init needs to be done before
  229. * machine_init functions access gpio APIs.
  230. * Hence omap7xx_gpio_init is a postcore_initcall.
  231. */
  232. static int __init omap7xx_gpio_init(void)
  233. {
  234. int i;
  235. if (!cpu_is_omap7xx())
  236. return -EINVAL;
  237. for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++)
  238. platform_device_register(omap7xx_gpio_dev[i]);
  239. return 0;
  240. }
  241. postcore_initcall(omap7xx_gpio_init);