dma.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * OMAP1/OMAP7xx - specific DMA driver
  4. *
  5. * Copyright (C) 2003 - 2008 Nokia Corporation
  6. * Author: Juha Yrjölä <[email protected]>
  7. * DMA channel linking for 1610 by Samuel Ortiz <[email protected]>
  8. * Graphics DMA and LCD DMA graphics tranformations
  9. * by Imre Deak <[email protected]>
  10. * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  11. * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12. *
  13. * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
  14. * Converted DMA library into platform driver
  15. * - G, Manjunath Kondaiah <[email protected]>
  16. */
  17. #include <linux/err.h>
  18. #include <linux/slab.h>
  19. #include <linux/module.h>
  20. #include <linux/init.h>
  21. #include <linux/device.h>
  22. #include <linux/io.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/dmaengine.h>
  25. #include <linux/omap-dma.h>
  26. #include "tc.h"
  27. #include "soc.h"
  28. #define OMAP1_DMA_BASE (0xfffed800)
  29. static u32 enable_1510_mode;
  30. static const struct omap_dma_reg reg_map[] = {
  31. [GCR] = { 0x0400, 0x00, OMAP_DMA_REG_16BIT },
  32. [GSCR] = { 0x0404, 0x00, OMAP_DMA_REG_16BIT },
  33. [GRST1] = { 0x0408, 0x00, OMAP_DMA_REG_16BIT },
  34. [HW_ID] = { 0x0442, 0x00, OMAP_DMA_REG_16BIT },
  35. [PCH2_ID] = { 0x0444, 0x00, OMAP_DMA_REG_16BIT },
  36. [PCH0_ID] = { 0x0446, 0x00, OMAP_DMA_REG_16BIT },
  37. [PCH1_ID] = { 0x0448, 0x00, OMAP_DMA_REG_16BIT },
  38. [PCHG_ID] = { 0x044a, 0x00, OMAP_DMA_REG_16BIT },
  39. [PCHD_ID] = { 0x044c, 0x00, OMAP_DMA_REG_16BIT },
  40. [CAPS_0] = { 0x044e, 0x00, OMAP_DMA_REG_2X16BIT },
  41. [CAPS_1] = { 0x0452, 0x00, OMAP_DMA_REG_2X16BIT },
  42. [CAPS_2] = { 0x0456, 0x00, OMAP_DMA_REG_16BIT },
  43. [CAPS_3] = { 0x0458, 0x00, OMAP_DMA_REG_16BIT },
  44. [CAPS_4] = { 0x045a, 0x00, OMAP_DMA_REG_16BIT },
  45. [PCH2_SR] = { 0x0460, 0x00, OMAP_DMA_REG_16BIT },
  46. [PCH0_SR] = { 0x0480, 0x00, OMAP_DMA_REG_16BIT },
  47. [PCH1_SR] = { 0x0482, 0x00, OMAP_DMA_REG_16BIT },
  48. [PCHD_SR] = { 0x04c0, 0x00, OMAP_DMA_REG_16BIT },
  49. /* Common Registers */
  50. [CSDP] = { 0x0000, 0x40, OMAP_DMA_REG_16BIT },
  51. [CCR] = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
  52. [CICR] = { 0x0004, 0x40, OMAP_DMA_REG_16BIT },
  53. [CSR] = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
  54. [CEN] = { 0x0010, 0x40, OMAP_DMA_REG_16BIT },
  55. [CFN] = { 0x0012, 0x40, OMAP_DMA_REG_16BIT },
  56. [CSFI] = { 0x0014, 0x40, OMAP_DMA_REG_16BIT },
  57. [CSEI] = { 0x0016, 0x40, OMAP_DMA_REG_16BIT },
  58. [CPC] = { 0x0018, 0x40, OMAP_DMA_REG_16BIT }, /* 15xx only */
  59. [CSAC] = { 0x0018, 0x40, OMAP_DMA_REG_16BIT },
  60. [CDAC] = { 0x001a, 0x40, OMAP_DMA_REG_16BIT },
  61. [CDEI] = { 0x001c, 0x40, OMAP_DMA_REG_16BIT },
  62. [CDFI] = { 0x001e, 0x40, OMAP_DMA_REG_16BIT },
  63. [CLNK_CTRL] = { 0x0028, 0x40, OMAP_DMA_REG_16BIT },
  64. /* Channel specific register offsets */
  65. [CSSA] = { 0x0008, 0x40, OMAP_DMA_REG_2X16BIT },
  66. [CDSA] = { 0x000c, 0x40, OMAP_DMA_REG_2X16BIT },
  67. [COLOR] = { 0x0020, 0x40, OMAP_DMA_REG_2X16BIT },
  68. [CCR2] = { 0x0024, 0x40, OMAP_DMA_REG_16BIT },
  69. [LCH_CTRL] = { 0x002a, 0x40, OMAP_DMA_REG_16BIT },
  70. };
  71. static struct resource res[] __initdata = {
  72. [0] = {
  73. .start = OMAP1_DMA_BASE,
  74. .end = OMAP1_DMA_BASE + SZ_2K - 1,
  75. .flags = IORESOURCE_MEM,
  76. },
  77. [1] = {
  78. .name = "0",
  79. .start = INT_DMA_CH0_6,
  80. .flags = IORESOURCE_IRQ,
  81. },
  82. [2] = {
  83. .name = "1",
  84. .start = INT_DMA_CH1_7,
  85. .flags = IORESOURCE_IRQ,
  86. },
  87. [3] = {
  88. .name = "2",
  89. .start = INT_DMA_CH2_8,
  90. .flags = IORESOURCE_IRQ,
  91. },
  92. [4] = {
  93. .name = "3",
  94. .start = INT_DMA_CH3,
  95. .flags = IORESOURCE_IRQ,
  96. },
  97. [5] = {
  98. .name = "4",
  99. .start = INT_DMA_CH4,
  100. .flags = IORESOURCE_IRQ,
  101. },
  102. [6] = {
  103. .name = "5",
  104. .start = INT_DMA_CH5,
  105. .flags = IORESOURCE_IRQ,
  106. },
  107. /* Handled in lcd_dma.c */
  108. [7] = {
  109. .name = "6",
  110. .start = INT_1610_DMA_CH6,
  111. .flags = IORESOURCE_IRQ,
  112. },
  113. /* irq's for omap16xx and omap7xx */
  114. [8] = {
  115. .name = "7",
  116. .start = INT_1610_DMA_CH7,
  117. .flags = IORESOURCE_IRQ,
  118. },
  119. [9] = {
  120. .name = "8",
  121. .start = INT_1610_DMA_CH8,
  122. .flags = IORESOURCE_IRQ,
  123. },
  124. [10] = {
  125. .name = "9",
  126. .start = INT_1610_DMA_CH9,
  127. .flags = IORESOURCE_IRQ,
  128. },
  129. [11] = {
  130. .name = "10",
  131. .start = INT_1610_DMA_CH10,
  132. .flags = IORESOURCE_IRQ,
  133. },
  134. [12] = {
  135. .name = "11",
  136. .start = INT_1610_DMA_CH11,
  137. .flags = IORESOURCE_IRQ,
  138. },
  139. [13] = {
  140. .name = "12",
  141. .start = INT_1610_DMA_CH12,
  142. .flags = IORESOURCE_IRQ,
  143. },
  144. [14] = {
  145. .name = "13",
  146. .start = INT_1610_DMA_CH13,
  147. .flags = IORESOURCE_IRQ,
  148. },
  149. [15] = {
  150. .name = "14",
  151. .start = INT_1610_DMA_CH14,
  152. .flags = IORESOURCE_IRQ,
  153. },
  154. [16] = {
  155. .name = "15",
  156. .start = INT_1610_DMA_CH15,
  157. .flags = IORESOURCE_IRQ,
  158. },
  159. [17] = {
  160. .name = "16",
  161. .start = INT_DMA_LCD,
  162. .flags = IORESOURCE_IRQ,
  163. },
  164. };
  165. static void __iomem *dma_base;
  166. static inline void dma_write(u32 val, int reg, int lch)
  167. {
  168. void __iomem *addr = dma_base;
  169. addr += reg_map[reg].offset;
  170. addr += reg_map[reg].stride * lch;
  171. __raw_writew(val, addr);
  172. if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
  173. __raw_writew(val >> 16, addr + 2);
  174. }
  175. static inline u32 dma_read(int reg, int lch)
  176. {
  177. void __iomem *addr = dma_base;
  178. uint32_t val;
  179. addr += reg_map[reg].offset;
  180. addr += reg_map[reg].stride * lch;
  181. val = __raw_readw(addr);
  182. if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
  183. val |= __raw_readw(addr + 2) << 16;
  184. return val;
  185. }
  186. static void omap1_clear_lch_regs(int lch)
  187. {
  188. int i;
  189. for (i = CPC; i <= COLOR; i += 1)
  190. dma_write(0, i, lch);
  191. }
  192. static void omap1_clear_dma(int lch)
  193. {
  194. u32 l;
  195. l = dma_read(CCR, lch);
  196. l &= ~OMAP_DMA_CCR_EN;
  197. dma_write(l, CCR, lch);
  198. /* Clear pending interrupts */
  199. l = dma_read(CSR, lch);
  200. }
  201. static void omap1_show_dma_caps(void)
  202. {
  203. if (enable_1510_mode) {
  204. printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
  205. } else {
  206. u16 w;
  207. printk(KERN_INFO "OMAP DMA hardware version %d\n",
  208. dma_read(HW_ID, 0));
  209. printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
  210. dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
  211. dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
  212. dma_read(CAPS_4, 0));
  213. /* Disable OMAP 3.0/3.1 compatibility mode. */
  214. w = dma_read(GSCR, 0);
  215. w |= 1 << 3;
  216. dma_write(w, GSCR, 0);
  217. }
  218. }
  219. static unsigned configure_dma_errata(void)
  220. {
  221. unsigned errata = 0;
  222. /*
  223. * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
  224. * read before the DMA controller finished disabling the channel.
  225. */
  226. if (!cpu_is_omap15xx())
  227. SET_DMA_ERRATA(DMA_ERRATA_3_3);
  228. return errata;
  229. }
  230. static const struct platform_device_info omap_dma_dev_info = {
  231. .name = "omap-dma-engine",
  232. .id = -1,
  233. .dma_mask = DMA_BIT_MASK(32),
  234. .res = res,
  235. .num_res = 1,
  236. };
  237. /* OMAP730, OMAP850 */
  238. static const struct dma_slave_map omap7xx_sdma_map[] = {
  239. { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) },
  240. { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) },
  241. { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(10) },
  242. { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(11) },
  243. { "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) },
  244. { "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) },
  245. { "omap_udc", "rx0", SDMA_FILTER_PARAM(26) },
  246. { "omap_udc", "rx1", SDMA_FILTER_PARAM(27) },
  247. { "omap_udc", "rx2", SDMA_FILTER_PARAM(28) },
  248. { "omap_udc", "tx0", SDMA_FILTER_PARAM(29) },
  249. { "omap_udc", "tx1", SDMA_FILTER_PARAM(30) },
  250. { "omap_udc", "tx2", SDMA_FILTER_PARAM(31) },
  251. };
  252. /* OMAP1510, OMAP1610*/
  253. static const struct dma_slave_map omap1xxx_sdma_map[] = {
  254. { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) },
  255. { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) },
  256. { "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(10) },
  257. { "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(11) },
  258. { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(16) },
  259. { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(17) },
  260. { "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) },
  261. { "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) },
  262. { "omap_udc", "rx0", SDMA_FILTER_PARAM(26) },
  263. { "omap_udc", "rx1", SDMA_FILTER_PARAM(27) },
  264. { "omap_udc", "rx2", SDMA_FILTER_PARAM(28) },
  265. { "omap_udc", "tx0", SDMA_FILTER_PARAM(29) },
  266. { "omap_udc", "tx1", SDMA_FILTER_PARAM(30) },
  267. { "omap_udc", "tx2", SDMA_FILTER_PARAM(31) },
  268. { "mmci-omap.1", "tx", SDMA_FILTER_PARAM(54) },
  269. { "mmci-omap.1", "rx", SDMA_FILTER_PARAM(55) },
  270. };
  271. static struct omap_system_dma_plat_info dma_plat_info __initdata = {
  272. .reg_map = reg_map,
  273. .channel_stride = 0x40,
  274. .show_dma_caps = omap1_show_dma_caps,
  275. .clear_lch_regs = omap1_clear_lch_regs,
  276. .clear_dma = omap1_clear_dma,
  277. .dma_write = dma_write,
  278. .dma_read = dma_read,
  279. };
  280. static int __init omap1_system_dma_init(void)
  281. {
  282. struct omap_system_dma_plat_info p;
  283. struct omap_dma_dev_attr *d;
  284. struct platform_device *pdev, *dma_pdev;
  285. int ret;
  286. pdev = platform_device_alloc("omap_dma_system", 0);
  287. if (!pdev) {
  288. pr_err("%s: Unable to device alloc for dma\n",
  289. __func__);
  290. return -ENOMEM;
  291. }
  292. dma_base = ioremap(res[0].start, resource_size(&res[0]));
  293. if (!dma_base) {
  294. pr_err("%s: Unable to ioremap\n", __func__);
  295. ret = -ENODEV;
  296. goto exit_device_put;
  297. }
  298. ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
  299. if (ret) {
  300. dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
  301. __func__, pdev->name, pdev->id);
  302. goto exit_iounmap;
  303. }
  304. d = kzalloc(sizeof(*d), GFP_KERNEL);
  305. if (!d) {
  306. ret = -ENOMEM;
  307. goto exit_iounmap;
  308. }
  309. /* Valid attributes for omap1 plus processors */
  310. if (cpu_is_omap15xx())
  311. d->dev_caps = ENABLE_1510_MODE;
  312. enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
  313. if (cpu_is_omap16xx())
  314. d->dev_caps = ENABLE_16XX_MODE;
  315. d->dev_caps |= SRC_PORT;
  316. d->dev_caps |= DST_PORT;
  317. d->dev_caps |= SRC_INDEX;
  318. d->dev_caps |= DST_INDEX;
  319. d->dev_caps |= IS_BURST_ONLY4;
  320. d->dev_caps |= CLEAR_CSR_ON_READ;
  321. d->dev_caps |= IS_WORD_16;
  322. /* available logical channels */
  323. if (cpu_is_omap15xx()) {
  324. d->lch_count = 9;
  325. } else {
  326. if (d->dev_caps & ENABLE_1510_MODE)
  327. d->lch_count = 9;
  328. else
  329. d->lch_count = 16;
  330. }
  331. p = dma_plat_info;
  332. p.dma_attr = d;
  333. p.errata = configure_dma_errata();
  334. if (cpu_is_omap7xx()) {
  335. p.slave_map = omap7xx_sdma_map;
  336. p.slavecnt = ARRAY_SIZE(omap7xx_sdma_map);
  337. } else {
  338. p.slave_map = omap1xxx_sdma_map;
  339. p.slavecnt = ARRAY_SIZE(omap1xxx_sdma_map);
  340. }
  341. ret = platform_device_add_data(pdev, &p, sizeof(p));
  342. if (ret) {
  343. dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
  344. __func__, pdev->name, pdev->id);
  345. goto exit_release_d;
  346. }
  347. ret = platform_device_add(pdev);
  348. if (ret) {
  349. dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
  350. __func__, pdev->name, pdev->id);
  351. goto exit_release_d;
  352. }
  353. dma_pdev = platform_device_register_full(&omap_dma_dev_info);
  354. if (IS_ERR(dma_pdev)) {
  355. ret = PTR_ERR(dma_pdev);
  356. goto exit_release_pdev;
  357. }
  358. return ret;
  359. exit_release_pdev:
  360. platform_device_del(pdev);
  361. exit_release_d:
  362. kfree(d);
  363. exit_iounmap:
  364. iounmap(dma_base);
  365. exit_device_put:
  366. platform_device_put(pdev);
  367. return ret;
  368. }
  369. arch_initcall(omap1_system_dma_init);