pmsu.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Power Management Service Unit(PMSU) support for Armada 370/XP platforms.
  4. *
  5. * Copyright (C) 2012 Marvell
  6. *
  7. * Yehuda Yitschak <[email protected]>
  8. * Gregory Clement <[email protected]>
  9. * Thomas Petazzoni <[email protected]>
  10. *
  11. * The Armada 370 and Armada XP SOCs have a power management service
  12. * unit which is responsible for powering down and waking up CPUs and
  13. * other SOC units
  14. */
  15. #define pr_fmt(fmt) "mvebu-pmsu: " fmt
  16. #include <linux/clk.h>
  17. #include <linux/cpu_pm.h>
  18. #include <linux/delay.h>
  19. #include <linux/init.h>
  20. #include <linux/io.h>
  21. #include <linux/kernel.h>
  22. #include <linux/mbus.h>
  23. #include <linux/mvebu-pmsu.h>
  24. #include <linux/of_address.h>
  25. #include <linux/of_device.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/resource.h>
  28. #include <linux/slab.h>
  29. #include <linux/smp.h>
  30. #include <asm/cacheflush.h>
  31. #include <asm/cp15.h>
  32. #include <asm/smp_scu.h>
  33. #include <asm/smp_plat.h>
  34. #include <asm/suspend.h>
  35. #include <asm/tlbflush.h>
  36. #include "common.h"
  37. #include "pmsu.h"
  38. #define PMSU_BASE_OFFSET 0x100
  39. #define PMSU_REG_SIZE 0x1000
  40. /* PMSU MP registers */
  41. #define PMSU_CONTROL_AND_CONFIG(cpu) ((cpu * 0x100) + 0x104)
  42. #define PMSU_CONTROL_AND_CONFIG_DFS_REQ BIT(18)
  43. #define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ BIT(16)
  44. #define PMSU_CONTROL_AND_CONFIG_L2_PWDDN BIT(20)
  45. #define PMSU_CPU_POWER_DOWN_CONTROL(cpu) ((cpu * 0x100) + 0x108)
  46. #define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP BIT(0)
  47. #define PMSU_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x10c)
  48. #define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT BIT(16)
  49. #define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT BIT(17)
  50. #define PMSU_STATUS_AND_MASK_IRQ_WAKEUP BIT(20)
  51. #define PMSU_STATUS_AND_MASK_FIQ_WAKEUP BIT(21)
  52. #define PMSU_STATUS_AND_MASK_DBG_WAKEUP BIT(22)
  53. #define PMSU_STATUS_AND_MASK_IRQ_MASK BIT(24)
  54. #define PMSU_STATUS_AND_MASK_FIQ_MASK BIT(25)
  55. #define PMSU_EVENT_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x120)
  56. #define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE BIT(1)
  57. #define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK BIT(17)
  58. #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)
  59. /* PMSU fabric registers */
  60. #define L2C_NFABRIC_PM_CTL 0x4
  61. #define L2C_NFABRIC_PM_CTL_PWR_DOWN BIT(20)
  62. /* PMSU delay registers */
  63. #define PMSU_POWERDOWN_DELAY 0xF04
  64. #define PMSU_POWERDOWN_DELAY_PMU BIT(1)
  65. #define PMSU_POWERDOWN_DELAY_MASK 0xFFFE
  66. #define PMSU_DFLT_ARMADA38X_DELAY 0x64
  67. /* CA9 MPcore SoC Control registers */
  68. #define MPCORE_RESET_CTL 0x64
  69. #define MPCORE_RESET_CTL_L2 BIT(0)
  70. #define MPCORE_RESET_CTL_DEBUG BIT(16)
  71. #define SRAM_PHYS_BASE 0xFFFF0000
  72. #define BOOTROM_BASE 0xFFF00000
  73. #define BOOTROM_SIZE 0x100000
  74. #define ARMADA_370_CRYPT0_ENG_TARGET 0x9
  75. #define ARMADA_370_CRYPT0_ENG_ATTR 0x1
  76. extern void ll_disable_coherency(void);
  77. extern void ll_enable_coherency(void);
  78. extern void armada_370_xp_cpu_resume(void);
  79. extern void armada_38x_cpu_resume(void);
  80. static phys_addr_t pmsu_mp_phys_base;
  81. static void __iomem *pmsu_mp_base;
  82. static void *mvebu_cpu_resume;
  83. static const struct of_device_id of_pmsu_table[] = {
  84. { .compatible = "marvell,armada-370-pmsu", },
  85. { .compatible = "marvell,armada-370-xp-pmsu", },
  86. { .compatible = "marvell,armada-380-pmsu", },
  87. { /* end of list */ },
  88. };
  89. void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
  90. {
  91. writel(__pa_symbol(boot_addr), pmsu_mp_base +
  92. PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
  93. }
  94. extern unsigned char mvebu_boot_wa_start[];
  95. extern unsigned char mvebu_boot_wa_end[];
  96. /*
  97. * This function sets up the boot address workaround needed for SMP
  98. * boot on Armada 375 Z1 and cpuidle on Armada 370. It unmaps the
  99. * BootROM Mbus window, and instead remaps a crypto SRAM into which a
  100. * custom piece of code is copied to replace the problematic BootROM.
  101. */
  102. int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
  103. unsigned int crypto_eng_attribute,
  104. phys_addr_t resume_addr_reg)
  105. {
  106. void __iomem *sram_virt_base;
  107. u32 code_len = mvebu_boot_wa_end - mvebu_boot_wa_start;
  108. mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
  109. mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute,
  110. SRAM_PHYS_BASE, SZ_64K);
  111. sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
  112. if (!sram_virt_base) {
  113. pr_err("Unable to map SRAM to setup the boot address WA\n");
  114. return -ENOMEM;
  115. }
  116. memcpy(sram_virt_base, &mvebu_boot_wa_start, code_len);
  117. /*
  118. * The last word of the code copied in SRAM must contain the
  119. * physical base address of the PMSU register. We
  120. * intentionally store this address in the native endianness
  121. * of the system.
  122. */
  123. __raw_writel((unsigned long)resume_addr_reg,
  124. sram_virt_base + code_len - 4);
  125. iounmap(sram_virt_base);
  126. return 0;
  127. }
  128. static int __init mvebu_v7_pmsu_init(void)
  129. {
  130. struct device_node *np;
  131. struct resource res;
  132. int ret = 0;
  133. np = of_find_matching_node(NULL, of_pmsu_table);
  134. if (!np)
  135. return 0;
  136. pr_info("Initializing Power Management Service Unit\n");
  137. if (of_address_to_resource(np, 0, &res)) {
  138. pr_err("unable to get resource\n");
  139. ret = -ENOENT;
  140. goto out;
  141. }
  142. if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) {
  143. pr_warn(FW_WARN "deprecated pmsu binding\n");
  144. res.start = res.start - PMSU_BASE_OFFSET;
  145. res.end = res.start + PMSU_REG_SIZE - 1;
  146. }
  147. if (!request_mem_region(res.start, resource_size(&res),
  148. np->full_name)) {
  149. pr_err("unable to request region\n");
  150. ret = -EBUSY;
  151. goto out;
  152. }
  153. pmsu_mp_phys_base = res.start;
  154. pmsu_mp_base = ioremap(res.start, resource_size(&res));
  155. if (!pmsu_mp_base) {
  156. pr_err("unable to map registers\n");
  157. release_mem_region(res.start, resource_size(&res));
  158. ret = -ENOMEM;
  159. goto out;
  160. }
  161. out:
  162. of_node_put(np);
  163. return ret;
  164. }
  165. static void mvebu_v7_pmsu_enable_l2_powerdown_onidle(void)
  166. {
  167. u32 reg;
  168. if (pmsu_mp_base == NULL)
  169. return;
  170. /* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */
  171. reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL);
  172. reg |= L2C_NFABRIC_PM_CTL_PWR_DOWN;
  173. writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
  174. }
  175. enum pmsu_idle_prepare_flags {
  176. PMSU_PREPARE_NORMAL = 0,
  177. PMSU_PREPARE_DEEP_IDLE = BIT(0),
  178. PMSU_PREPARE_SNOOP_DISABLE = BIT(1),
  179. };
  180. /* No locking is needed because we only access per-CPU registers */
  181. static int mvebu_v7_pmsu_idle_prepare(unsigned long flags)
  182. {
  183. unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
  184. u32 reg;
  185. if (pmsu_mp_base == NULL)
  186. return -EINVAL;
  187. /*
  188. * Adjust the PMSU configuration to wait for WFI signal, enable
  189. * IRQ and FIQ as wakeup events, set wait for snoop queue empty
  190. * indication and mask IRQ and FIQ from CPU
  191. */
  192. reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
  193. reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT |
  194. PMSU_STATUS_AND_MASK_IRQ_WAKEUP |
  195. PMSU_STATUS_AND_MASK_FIQ_WAKEUP |
  196. PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT |
  197. PMSU_STATUS_AND_MASK_IRQ_MASK |
  198. PMSU_STATUS_AND_MASK_FIQ_MASK;
  199. writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
  200. reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
  201. /* ask HW to power down the L2 Cache if needed */
  202. if (flags & PMSU_PREPARE_DEEP_IDLE)
  203. reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
  204. /* request power down */
  205. reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
  206. writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
  207. if (flags & PMSU_PREPARE_SNOOP_DISABLE) {
  208. /* Disable snoop disable by HW - SW is taking care of it */
  209. reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
  210. reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
  211. writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
  212. }
  213. return 0;
  214. }
  215. int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
  216. {
  217. unsigned long flags = PMSU_PREPARE_SNOOP_DISABLE;
  218. int ret;
  219. if (deepidle)
  220. flags |= PMSU_PREPARE_DEEP_IDLE;
  221. ret = mvebu_v7_pmsu_idle_prepare(flags);
  222. if (ret)
  223. return ret;
  224. v7_exit_coherency_flush(all);
  225. ll_disable_coherency();
  226. dsb();
  227. wfi();
  228. /* If we are here, wfi failed. As processors run out of
  229. * coherency for some time, tlbs might be stale, so flush them
  230. */
  231. local_flush_tlb_all();
  232. ll_enable_coherency();
  233. /* Test the CR_C bit and set it if it was cleared */
  234. asm volatile(
  235. "mrc p15, 0, r0, c1, c0, 0 \n\t"
  236. "tst r0, %0 \n\t"
  237. "orreq r0, r0, #(1 << 2) \n\t"
  238. "mcreq p15, 0, r0, c1, c0, 0 \n\t"
  239. "isb "
  240. : : "Ir" (CR_C) : "r0");
  241. pr_debug("Failed to suspend the system\n");
  242. return 0;
  243. }
  244. static int armada_370_xp_cpu_suspend(unsigned long deepidle)
  245. {
  246. return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter);
  247. }
  248. int armada_38x_do_cpu_suspend(unsigned long deepidle)
  249. {
  250. unsigned long flags = 0;
  251. if (deepidle)
  252. flags |= PMSU_PREPARE_DEEP_IDLE;
  253. mvebu_v7_pmsu_idle_prepare(flags);
  254. /*
  255. * Already flushed cache, but do it again as the outer cache
  256. * functions dirty the cache with spinlocks
  257. */
  258. v7_exit_coherency_flush(louis);
  259. scu_power_mode(mvebu_get_scu_base(), SCU_PM_POWEROFF);
  260. cpu_do_idle();
  261. return 1;
  262. }
  263. static int armada_38x_cpu_suspend(unsigned long deepidle)
  264. {
  265. return cpu_suspend(false, armada_38x_do_cpu_suspend);
  266. }
  267. /* No locking is needed because we only access per-CPU registers */
  268. void mvebu_v7_pmsu_idle_exit(void)
  269. {
  270. unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
  271. u32 reg;
  272. if (pmsu_mp_base == NULL)
  273. return;
  274. /* cancel ask HW to power down the L2 Cache if possible */
  275. reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
  276. reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
  277. writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
  278. /* cancel Enable wakeup events and mask interrupts */
  279. reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
  280. reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP | PMSU_STATUS_AND_MASK_FIQ_WAKEUP);
  281. reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
  282. reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT;
  283. reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK | PMSU_STATUS_AND_MASK_FIQ_MASK);
  284. writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
  285. }
  286. static int mvebu_v7_cpu_pm_notify(struct notifier_block *self,
  287. unsigned long action, void *hcpu)
  288. {
  289. if (action == CPU_PM_ENTER) {
  290. unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
  291. mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cpu_resume);
  292. } else if (action == CPU_PM_EXIT) {
  293. mvebu_v7_pmsu_idle_exit();
  294. }
  295. return NOTIFY_OK;
  296. }
  297. static struct notifier_block mvebu_v7_cpu_pm_notifier = {
  298. .notifier_call = mvebu_v7_cpu_pm_notify,
  299. };
  300. static struct platform_device mvebu_v7_cpuidle_device;
  301. static int broken_idle(struct device_node *np)
  302. {
  303. if (of_property_read_bool(np, "broken-idle")) {
  304. pr_warn("CPU idle is currently broken: disabling\n");
  305. return 1;
  306. }
  307. return 0;
  308. }
  309. static __init int armada_370_cpuidle_init(void)
  310. {
  311. struct device_node *np;
  312. phys_addr_t redirect_reg;
  313. np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
  314. if (!np)
  315. return -ENODEV;
  316. if (broken_idle(np))
  317. goto end;
  318. /*
  319. * On Armada 370, there is "a slow exit process from the deep
  320. * idle state due to heavy L1/L2 cache cleanup operations
  321. * performed by the BootROM software". To avoid this, we
  322. * replace the restart code of the bootrom by a a simple jump
  323. * to the boot address. Then the code located at this boot
  324. * address will take care of the initialization.
  325. */
  326. redirect_reg = pmsu_mp_phys_base + PMSU_BOOT_ADDR_REDIRECT_OFFSET(0);
  327. mvebu_setup_boot_addr_wa(ARMADA_370_CRYPT0_ENG_TARGET,
  328. ARMADA_370_CRYPT0_ENG_ATTR,
  329. redirect_reg);
  330. mvebu_cpu_resume = armada_370_xp_cpu_resume;
  331. mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
  332. mvebu_v7_cpuidle_device.name = "cpuidle-armada-370";
  333. end:
  334. of_node_put(np);
  335. return 0;
  336. }
  337. static __init int armada_38x_cpuidle_init(void)
  338. {
  339. struct device_node *np;
  340. void __iomem *mpsoc_base;
  341. u32 reg;
  342. pr_warn("CPU idle is currently broken on Armada 38x: disabling\n");
  343. return 0;
  344. np = of_find_compatible_node(NULL, NULL,
  345. "marvell,armada-380-coherency-fabric");
  346. if (!np)
  347. return -ENODEV;
  348. if (broken_idle(np))
  349. goto end;
  350. of_node_put(np);
  351. np = of_find_compatible_node(NULL, NULL,
  352. "marvell,armada-380-mpcore-soc-ctrl");
  353. if (!np)
  354. return -ENODEV;
  355. mpsoc_base = of_iomap(np, 0);
  356. BUG_ON(!mpsoc_base);
  357. /* Set up reset mask when powering down the cpus */
  358. reg = readl(mpsoc_base + MPCORE_RESET_CTL);
  359. reg |= MPCORE_RESET_CTL_L2;
  360. reg |= MPCORE_RESET_CTL_DEBUG;
  361. writel(reg, mpsoc_base + MPCORE_RESET_CTL);
  362. iounmap(mpsoc_base);
  363. /* Set up delay */
  364. reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY);
  365. reg &= ~PMSU_POWERDOWN_DELAY_MASK;
  366. reg |= PMSU_DFLT_ARMADA38X_DELAY;
  367. reg |= PMSU_POWERDOWN_DELAY_PMU;
  368. writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY);
  369. mvebu_cpu_resume = armada_38x_cpu_resume;
  370. mvebu_v7_cpuidle_device.dev.platform_data = armada_38x_cpu_suspend;
  371. mvebu_v7_cpuidle_device.name = "cpuidle-armada-38x";
  372. end:
  373. of_node_put(np);
  374. return 0;
  375. }
  376. static __init int armada_xp_cpuidle_init(void)
  377. {
  378. struct device_node *np;
  379. np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
  380. if (!np)
  381. return -ENODEV;
  382. if (broken_idle(np))
  383. goto end;
  384. mvebu_cpu_resume = armada_370_xp_cpu_resume;
  385. mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
  386. mvebu_v7_cpuidle_device.name = "cpuidle-armada-xp";
  387. end:
  388. of_node_put(np);
  389. return 0;
  390. }
  391. static int __init mvebu_v7_cpu_pm_init(void)
  392. {
  393. struct device_node *np;
  394. int ret;
  395. np = of_find_matching_node(NULL, of_pmsu_table);
  396. if (!np)
  397. return 0;
  398. of_node_put(np);
  399. /*
  400. * Currently the CPU idle support for Armada 38x is broken, as
  401. * the CPU hotplug uses some of the CPU idle functions it is
  402. * broken too, so let's disable it
  403. */
  404. if (of_machine_is_compatible("marvell,armada380")) {
  405. cpu_hotplug_disable();
  406. pr_warn("CPU hotplug support is currently broken on Armada 38x: disabling\n");
  407. }
  408. if (of_machine_is_compatible("marvell,armadaxp"))
  409. ret = armada_xp_cpuidle_init();
  410. else if (of_machine_is_compatible("marvell,armada370"))
  411. ret = armada_370_cpuidle_init();
  412. else if (of_machine_is_compatible("marvell,armada380"))
  413. ret = armada_38x_cpuidle_init();
  414. else
  415. return 0;
  416. if (ret)
  417. return ret;
  418. mvebu_v7_pmsu_enable_l2_powerdown_onidle();
  419. if (mvebu_v7_cpuidle_device.name)
  420. platform_device_register(&mvebu_v7_cpuidle_device);
  421. cpu_pm_register_notifier(&mvebu_v7_cpu_pm_notifier);
  422. return 0;
  423. }
  424. arch_initcall(mvebu_v7_cpu_pm_init);
  425. early_initcall(mvebu_v7_pmsu_init);
  426. static void mvebu_pmsu_dfs_request_local(void *data)
  427. {
  428. u32 reg;
  429. u32 cpu = smp_processor_id();
  430. unsigned long flags;
  431. local_irq_save(flags);
  432. /* Prepare to enter idle */
  433. reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
  434. reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT |
  435. PMSU_STATUS_AND_MASK_IRQ_MASK |
  436. PMSU_STATUS_AND_MASK_FIQ_MASK;
  437. writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
  438. /* Request the DFS transition */
  439. reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
  440. reg |= PMSU_CONTROL_AND_CONFIG_DFS_REQ;
  441. writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
  442. /* The fact of entering idle will trigger the DFS transition */
  443. wfi();
  444. /*
  445. * We're back from idle, the DFS transition has completed,
  446. * clear the idle wait indication.
  447. */
  448. reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
  449. reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
  450. writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
  451. local_irq_restore(flags);
  452. }
  453. int mvebu_pmsu_dfs_request(int cpu)
  454. {
  455. unsigned long timeout;
  456. int hwcpu = cpu_logical_map(cpu);
  457. u32 reg;
  458. /* Clear any previous DFS DONE event */
  459. reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
  460. reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE;
  461. writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
  462. /* Mask the DFS done interrupt, since we are going to poll */
  463. reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
  464. reg |= PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
  465. writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
  466. /* Trigger the DFS on the appropriate CPU */
  467. smp_call_function_single(cpu, mvebu_pmsu_dfs_request_local,
  468. NULL, false);
  469. /* Poll until the DFS done event is generated */
  470. timeout = jiffies + HZ;
  471. while (time_before(jiffies, timeout)) {
  472. reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
  473. if (reg & PMSU_EVENT_STATUS_AND_MASK_DFS_DONE)
  474. break;
  475. udelay(10);
  476. }
  477. if (time_after(jiffies, timeout))
  478. return -ETIME;
  479. /* Restore the DFS mask to its original state */
  480. reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
  481. reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
  482. writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
  483. return 0;
  484. }