time.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/mach-mmp/time.c
  4. *
  5. * Support for clocksource and clockevents
  6. *
  7. * Copyright (C) 2008 Marvell International Ltd.
  8. * All rights reserved.
  9. *
  10. * 2008-04-11: Jason Chagas <[email protected]>
  11. * 2008-10-08: Bin Yang <[email protected]>
  12. *
  13. * The timers module actually includes three timers, each timer with up to
  14. * three match comparators. Timer #0 is used here in free-running mode as
  15. * the clock source, and match comparator #1 used as clock event device.
  16. */
  17. #include <linux/init.h>
  18. #include <linux/kernel.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/clockchips.h>
  21. #include <linux/clk.h>
  22. #include <linux/io.h>
  23. #include <linux/irq.h>
  24. #include <linux/of.h>
  25. #include <linux/of_address.h>
  26. #include <linux/of_irq.h>
  27. #include <linux/sched_clock.h>
  28. #include <asm/mach/time.h>
  29. #include "addr-map.h"
  30. #include "regs-timers.h"
  31. #include "regs-apbc.h"
  32. #include "irqs.h"
  33. #include <linux/soc/mmp/cputype.h>
  34. #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
  35. #define MAX_DELTA (0xfffffffe)
  36. #define MIN_DELTA (16)
  37. static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
  38. /*
  39. * Read the timer through the CVWR register. Delay is required after requesting
  40. * a read. The CR register cannot be directly read due to metastability issues
  41. * documented in the PXA168 software manual.
  42. */
  43. static inline uint32_t timer_read(void)
  44. {
  45. uint32_t val;
  46. int delay = 3;
  47. __raw_writel(1, mmp_timer_base + TMR_CVWR(1));
  48. while (delay--)
  49. val = __raw_readl(mmp_timer_base + TMR_CVWR(1));
  50. return val;
  51. }
  52. static u64 notrace mmp_read_sched_clock(void)
  53. {
  54. return timer_read();
  55. }
  56. static irqreturn_t timer_interrupt(int irq, void *dev_id)
  57. {
  58. struct clock_event_device *c = dev_id;
  59. /*
  60. * Clear pending interrupt status.
  61. */
  62. __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
  63. /*
  64. * Disable timer 0.
  65. */
  66. __raw_writel(0x02, mmp_timer_base + TMR_CER);
  67. c->event_handler(c);
  68. return IRQ_HANDLED;
  69. }
  70. static int timer_set_next_event(unsigned long delta,
  71. struct clock_event_device *dev)
  72. {
  73. unsigned long flags;
  74. local_irq_save(flags);
  75. /*
  76. * Disable timer 0.
  77. */
  78. __raw_writel(0x02, mmp_timer_base + TMR_CER);
  79. /*
  80. * Clear and enable timer match 0 interrupt.
  81. */
  82. __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
  83. __raw_writel(0x01, mmp_timer_base + TMR_IER(0));
  84. /*
  85. * Setup new clockevent timer value.
  86. */
  87. __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
  88. /*
  89. * Enable timer 0.
  90. */
  91. __raw_writel(0x03, mmp_timer_base + TMR_CER);
  92. local_irq_restore(flags);
  93. return 0;
  94. }
  95. static int timer_set_shutdown(struct clock_event_device *evt)
  96. {
  97. unsigned long flags;
  98. local_irq_save(flags);
  99. /* disable the matching interrupt */
  100. __raw_writel(0x00, mmp_timer_base + TMR_IER(0));
  101. local_irq_restore(flags);
  102. return 0;
  103. }
  104. static struct clock_event_device ckevt = {
  105. .name = "clockevent",
  106. .features = CLOCK_EVT_FEAT_ONESHOT,
  107. .rating = 200,
  108. .set_next_event = timer_set_next_event,
  109. .set_state_shutdown = timer_set_shutdown,
  110. .set_state_oneshot = timer_set_shutdown,
  111. };
  112. static u64 clksrc_read(struct clocksource *cs)
  113. {
  114. return timer_read();
  115. }
  116. static struct clocksource cksrc = {
  117. .name = "clocksource",
  118. .rating = 200,
  119. .read = clksrc_read,
  120. .mask = CLOCKSOURCE_MASK(32),
  121. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  122. };
  123. static void __init timer_config(void)
  124. {
  125. uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
  126. __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
  127. ccr &= (cpu_is_mmp2() || cpu_is_mmp3()) ?
  128. (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
  129. (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
  130. __raw_writel(ccr, mmp_timer_base + TMR_CCR);
  131. /* set timer 0 to periodic mode, and timer 1 to free-running mode */
  132. __raw_writel(0x2, mmp_timer_base + TMR_CMR);
  133. __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
  134. __raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */
  135. __raw_writel(0x0, mmp_timer_base + TMR_IER(0));
  136. __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
  137. __raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */
  138. __raw_writel(0x0, mmp_timer_base + TMR_IER(1));
  139. /* enable timer 1 counter */
  140. __raw_writel(0x2, mmp_timer_base + TMR_CER);
  141. }
  142. void __init mmp_timer_init(int irq, unsigned long rate)
  143. {
  144. timer_config();
  145. sched_clock_register(mmp_read_sched_clock, 32, rate);
  146. ckevt.cpumask = cpumask_of(0);
  147. if (request_irq(irq, timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
  148. "timer", &ckevt))
  149. pr_err("Failed to request irq %d (timer)\n", irq);
  150. clocksource_register_hz(&cksrc, rate);
  151. clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA);
  152. }
  153. static int __init mmp_dt_init_timer(struct device_node *np)
  154. {
  155. struct clk *clk;
  156. int irq, ret;
  157. unsigned long rate;
  158. clk = of_clk_get(np, 0);
  159. if (!IS_ERR(clk)) {
  160. ret = clk_prepare_enable(clk);
  161. if (ret)
  162. return ret;
  163. rate = clk_get_rate(clk);
  164. } else if (cpu_is_pj4()) {
  165. rate = 6500000;
  166. } else {
  167. rate = 3250000;
  168. }
  169. irq = irq_of_parse_and_map(np, 0);
  170. if (!irq)
  171. return -EINVAL;
  172. mmp_timer_base = of_iomap(np, 0);
  173. if (!mmp_timer_base)
  174. return -ENOMEM;
  175. mmp_timer_init(irq, rate);
  176. return 0;
  177. }
  178. TIMER_OF_DECLARE(mmp_timer, "mrvl,mmp-timer", mmp_dt_init_timer);