pxa910.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/mach-mmp/pxa910.c
  4. *
  5. * Code specific to PXA910
  6. */
  7. #include <linux/clk/mmp.h>
  8. #include <linux/module.h>
  9. #include <linux/kernel.h>
  10. #include <linux/init.h>
  11. #include <linux/list.h>
  12. #include <linux/io.h>
  13. #include <linux/irq.h>
  14. #include <linux/irqchip/mmp.h>
  15. #include <linux/platform_device.h>
  16. #include <asm/hardware/cache-tauros2.h>
  17. #include <asm/mach/time.h>
  18. #include "addr-map.h"
  19. #include "regs-apbc.h"
  20. #include <linux/soc/mmp/cputype.h>
  21. #include "irqs.h"
  22. #include "mfp.h"
  23. #include "devices.h"
  24. #include "pm-pxa910.h"
  25. #include "pxa910.h"
  26. #include "common.h"
  27. #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
  28. static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata =
  29. {
  30. MFP_ADDR_X(GPIO0, GPIO54, 0xdc),
  31. MFP_ADDR_X(GPIO67, GPIO98, 0x1b8),
  32. MFP_ADDR_X(GPIO100, GPIO109, 0x238),
  33. MFP_ADDR(GPIO123, 0xcc),
  34. MFP_ADDR(GPIO124, 0xd0),
  35. MFP_ADDR(DF_IO0, 0x40),
  36. MFP_ADDR(DF_IO1, 0x3c),
  37. MFP_ADDR(DF_IO2, 0x38),
  38. MFP_ADDR(DF_IO3, 0x34),
  39. MFP_ADDR(DF_IO4, 0x30),
  40. MFP_ADDR(DF_IO5, 0x2c),
  41. MFP_ADDR(DF_IO6, 0x28),
  42. MFP_ADDR(DF_IO7, 0x24),
  43. MFP_ADDR(DF_IO8, 0x20),
  44. MFP_ADDR(DF_IO9, 0x1c),
  45. MFP_ADDR(DF_IO10, 0x18),
  46. MFP_ADDR(DF_IO11, 0x14),
  47. MFP_ADDR(DF_IO12, 0x10),
  48. MFP_ADDR(DF_IO13, 0xc),
  49. MFP_ADDR(DF_IO14, 0x8),
  50. MFP_ADDR(DF_IO15, 0x4),
  51. MFP_ADDR(DF_nCS0_SM_nCS2, 0x44),
  52. MFP_ADDR(DF_nCS1_SM_nCS3, 0x48),
  53. MFP_ADDR(SM_nCS0, 0x4c),
  54. MFP_ADDR(SM_nCS1, 0x50),
  55. MFP_ADDR(DF_WEn, 0x54),
  56. MFP_ADDR(DF_REn, 0x58),
  57. MFP_ADDR(DF_CLE_SM_OEn, 0x5c),
  58. MFP_ADDR(DF_ALE_SM_WEn, 0x60),
  59. MFP_ADDR(SM_SCLK, 0x64),
  60. MFP_ADDR(DF_RDY0, 0x68),
  61. MFP_ADDR(SM_BE0, 0x6c),
  62. MFP_ADDR(SM_BE1, 0x70),
  63. MFP_ADDR(SM_ADV, 0x74),
  64. MFP_ADDR(DF_RDY1, 0x78),
  65. MFP_ADDR(SM_ADVMUX, 0x7c),
  66. MFP_ADDR(SM_RDY, 0x80),
  67. MFP_ADDR_X(MMC1_DAT7, MMC1_WP, 0x84),
  68. MFP_ADDR_END,
  69. };
  70. void __init pxa910_init_irq(void)
  71. {
  72. icu_init_irq();
  73. #ifdef CONFIG_PM
  74. icu_irq_chip.irq_set_wake = pxa910_set_wake;
  75. #endif
  76. }
  77. static int __init pxa910_init(void)
  78. {
  79. if (cpu_is_pxa910()) {
  80. #ifdef CONFIG_CACHE_TAUROS2
  81. tauros2_init(0);
  82. #endif
  83. mfp_init_base(MFPR_VIRT_BASE);
  84. mfp_init_addr(pxa910_mfp_addr_map);
  85. pxa910_clk_init(APB_PHYS_BASE + 0x50000,
  86. AXI_PHYS_BASE + 0x82800,
  87. APB_PHYS_BASE + 0x15000,
  88. APB_PHYS_BASE + 0x3b000);
  89. }
  90. return 0;
  91. }
  92. postcore_initcall(pxa910_init);
  93. /* system timer - clock enabled, 3.25MHz */
  94. #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
  95. #define APBC_TIMERS APBC_REG(0x34)
  96. void __init pxa910_timer_init(void)
  97. {
  98. /* reset and configure */
  99. __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
  100. __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
  101. mmp_timer_init(IRQ_PXA910_AP1_TIMER1, 3250000);
  102. }
  103. /* on-chip devices */
  104. /* NOTE: there are totally 3 UARTs on PXA910:
  105. *
  106. * UART1 - Slow UART (can be used both by AP and CP)
  107. * UART2/3 - Fast UART
  108. *
  109. * To be backward compatible with the legacy FFUART/BTUART/STUART sequence,
  110. * they are re-ordered as:
  111. *
  112. * pxa910_device_uart1 - UART2 as FFUART
  113. * pxa910_device_uart2 - UART3 as BTUART
  114. *
  115. * UART1 is not used by AP for the moment.
  116. */
  117. PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22);
  118. PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24);
  119. PXA910_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28);
  120. PXA910_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28);
  121. PXA910_DEVICE(pwm1, "pxa910-pwm", 0, NONE, 0xd401a000, 0x10);
  122. PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10);
  123. PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10);
  124. PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10);
  125. PXA910_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99);
  126. PXA910_DEVICE(disp, "mmp-disp", 0, LCD, 0xd420b000, 0x1ec);
  127. PXA910_DEVICE(fb, "mmp-fb", -1, NONE, 0, 0);
  128. PXA910_DEVICE(panel, "tpo-hvga", -1, NONE, 0, 0);
  129. struct resource pxa910_resource_gpio[] = {
  130. {
  131. .start = 0xd4019000,
  132. .end = 0xd4019fff,
  133. .flags = IORESOURCE_MEM,
  134. }, {
  135. .start = IRQ_PXA910_AP_GPIO,
  136. .end = IRQ_PXA910_AP_GPIO,
  137. .name = "gpio_mux",
  138. .flags = IORESOURCE_IRQ,
  139. },
  140. };
  141. struct platform_device pxa910_device_gpio = {
  142. .name = "mmp-gpio",
  143. .id = -1,
  144. .num_resources = ARRAY_SIZE(pxa910_resource_gpio),
  145. .resource = pxa910_resource_gpio,
  146. };
  147. static struct resource pxa910_resource_rtc[] = {
  148. {
  149. .start = 0xd4010000,
  150. .end = 0xd401003f,
  151. .flags = IORESOURCE_MEM,
  152. }, {
  153. .start = IRQ_PXA910_RTC_INT,
  154. .end = IRQ_PXA910_RTC_INT,
  155. .name = "rtc 1Hz",
  156. .flags = IORESOURCE_IRQ,
  157. }, {
  158. .start = IRQ_PXA910_RTC_ALARM,
  159. .end = IRQ_PXA910_RTC_ALARM,
  160. .name = "rtc alarm",
  161. .flags = IORESOURCE_IRQ,
  162. },
  163. };
  164. struct platform_device pxa910_device_rtc = {
  165. .name = "sa1100-rtc",
  166. .id = -1,
  167. .num_resources = ARRAY_SIZE(pxa910_resource_rtc),
  168. .resource = pxa910_resource_rtc,
  169. };