mmp2.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/mach-mmp/mmp2.c
  4. *
  5. * code name MMP2
  6. *
  7. * Copyright (C) 2009 Marvell International Ltd.
  8. */
  9. #include <linux/clk/mmp.h>
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/init.h>
  13. #include <linux/io.h>
  14. #include <linux/irq.h>
  15. #include <linux/irqchip/mmp.h>
  16. #include <linux/platform_device.h>
  17. #include <asm/hardware/cache-tauros2.h>
  18. #include <asm/mach/time.h>
  19. #include "addr-map.h"
  20. #include "regs-apbc.h"
  21. #include <linux/soc/mmp/cputype.h>
  22. #include "irqs.h"
  23. #include "mfp.h"
  24. #include "devices.h"
  25. #include "mmp2.h"
  26. #include "pm-mmp2.h"
  27. #include "common.h"
  28. #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
  29. static struct mfp_addr_map mmp2_addr_map[] __initdata = {
  30. MFP_ADDR_X(GPIO0, GPIO58, 0x54),
  31. MFP_ADDR_X(GPIO59, GPIO73, 0x280),
  32. MFP_ADDR_X(GPIO74, GPIO101, 0x170),
  33. MFP_ADDR(GPIO102, 0x0),
  34. MFP_ADDR(GPIO103, 0x4),
  35. MFP_ADDR(GPIO104, 0x1fc),
  36. MFP_ADDR(GPIO105, 0x1f8),
  37. MFP_ADDR(GPIO106, 0x1f4),
  38. MFP_ADDR(GPIO107, 0x1f0),
  39. MFP_ADDR(GPIO108, 0x21c),
  40. MFP_ADDR(GPIO109, 0x218),
  41. MFP_ADDR(GPIO110, 0x214),
  42. MFP_ADDR(GPIO111, 0x200),
  43. MFP_ADDR(GPIO112, 0x244),
  44. MFP_ADDR(GPIO113, 0x25c),
  45. MFP_ADDR(GPIO114, 0x164),
  46. MFP_ADDR_X(GPIO115, GPIO122, 0x260),
  47. MFP_ADDR(GPIO123, 0x148),
  48. MFP_ADDR_X(GPIO124, GPIO141, 0xc),
  49. MFP_ADDR(GPIO142, 0x8),
  50. MFP_ADDR_X(GPIO143, GPIO151, 0x220),
  51. MFP_ADDR_X(GPIO152, GPIO153, 0x248),
  52. MFP_ADDR_X(GPIO154, GPIO155, 0x254),
  53. MFP_ADDR_X(GPIO156, GPIO159, 0x14c),
  54. MFP_ADDR(GPIO160, 0x250),
  55. MFP_ADDR(GPIO161, 0x210),
  56. MFP_ADDR(GPIO162, 0x20c),
  57. MFP_ADDR(GPIO163, 0x208),
  58. MFP_ADDR(GPIO164, 0x204),
  59. MFP_ADDR(GPIO165, 0x1ec),
  60. MFP_ADDR(GPIO166, 0x1e8),
  61. MFP_ADDR(GPIO167, 0x1e4),
  62. MFP_ADDR(GPIO168, 0x1e0),
  63. MFP_ADDR_X(TWSI1_SCL, TWSI1_SDA, 0x140),
  64. MFP_ADDR_X(TWSI4_SCL, TWSI4_SDA, 0x2bc),
  65. MFP_ADDR(PMIC_INT, 0x2c4),
  66. MFP_ADDR(CLK_REQ, 0x160),
  67. MFP_ADDR_END,
  68. };
  69. void mmp2_clear_pmic_int(void)
  70. {
  71. void __iomem *mfpr_pmic;
  72. unsigned long data;
  73. mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4;
  74. data = __raw_readl(mfpr_pmic);
  75. __raw_writel(data | (1 << 6), mfpr_pmic);
  76. __raw_writel(data, mfpr_pmic);
  77. }
  78. void __init mmp2_init_irq(void)
  79. {
  80. mmp2_init_icu();
  81. #ifdef CONFIG_PM
  82. icu_irq_chip.irq_set_wake = mmp2_set_wake;
  83. #endif
  84. }
  85. static int __init mmp2_init(void)
  86. {
  87. if (cpu_is_mmp2()) {
  88. #ifdef CONFIG_CACHE_TAUROS2
  89. tauros2_init(0);
  90. #endif
  91. mfp_init_base(MFPR_VIRT_BASE);
  92. mfp_init_addr(mmp2_addr_map);
  93. mmp2_clk_init(APB_PHYS_BASE + 0x50000,
  94. AXI_PHYS_BASE + 0x82800,
  95. APB_PHYS_BASE + 0x15000);
  96. }
  97. return 0;
  98. }
  99. postcore_initcall(mmp2_init);
  100. #define APBC_TIMERS APBC_REG(0x024)
  101. void __init mmp2_timer_init(void)
  102. {
  103. unsigned long clk_rst;
  104. __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
  105. /*
  106. * enable bus/functional clock, enable 6.5MHz (divider 4),
  107. * release reset
  108. */
  109. clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
  110. __raw_writel(clk_rst, APBC_TIMERS);
  111. mmp_timer_init(IRQ_MMP2_TIMER1, 6500000);
  112. }
  113. /* on-chip devices */
  114. MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5);
  115. MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21);
  116. MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23);
  117. MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19);
  118. MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70);
  119. MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70);
  120. MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70);
  121. MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
  122. MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
  123. MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
  124. MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
  125. MMP2_DEVICE(sdh0, "sdhci-pxav3", 0, MMC, 0xd4280000, 0x120);
  126. MMP2_DEVICE(sdh1, "sdhci-pxav3", 1, MMC2, 0xd4280800, 0x120);
  127. MMP2_DEVICE(sdh2, "sdhci-pxav3", 2, MMC3, 0xd4281000, 0x120);
  128. MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120);
  129. MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000);
  130. /* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */
  131. MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000);
  132. struct resource mmp2_resource_gpio[] = {
  133. {
  134. .start = 0xd4019000,
  135. .end = 0xd4019fff,
  136. .flags = IORESOURCE_MEM,
  137. }, {
  138. .start = IRQ_MMP2_GPIO,
  139. .end = IRQ_MMP2_GPIO,
  140. .name = "gpio_mux",
  141. .flags = IORESOURCE_IRQ,
  142. },
  143. };
  144. struct platform_device mmp2_device_gpio = {
  145. .name = "mmp2-gpio",
  146. .id = -1,
  147. .num_resources = ARRAY_SIZE(mmp2_resource_gpio),
  148. .resource = mmp2_resource_gpio,
  149. };