pci.c 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * arch/arm/plat-iop/pci.c
  4. *
  5. * PCI support for the Intel IOP32X and IOP33X processors
  6. *
  7. * Author: Rory Bolt <[email protected]>
  8. * Copyright (C) 2002 Rory Bolt
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/pci.h>
  12. #include <linux/slab.h>
  13. #include <linux/mm.h>
  14. #include <linux/init.h>
  15. #include <linux/ioport.h>
  16. #include <linux/io.h>
  17. #include <asm/irq.h>
  18. #include <asm/signal.h>
  19. #include <asm/mach/pci.h>
  20. #include "hardware.h"
  21. #include "iop3xx.h"
  22. // #define DEBUG
  23. #ifdef DEBUG
  24. #define DBG(x...) printk(x)
  25. #else
  26. #define DBG(x...) do { } while (0)
  27. #endif
  28. /*
  29. * This routine builds either a type0 or type1 configuration command. If the
  30. * bus is on the 803xx then a type0 made, else a type1 is created.
  31. */
  32. static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where)
  33. {
  34. struct pci_sys_data *sys = bus->sysdata;
  35. u32 addr;
  36. if (sys->busnr == bus->number)
  37. addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
  38. else
  39. addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
  40. addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
  41. return addr;
  42. }
  43. /*
  44. * This routine checks the status of the last configuration cycle. If an error
  45. * was detected it returns a 1, else it returns a 0. The errors being checked
  46. * are parity, master abort, target abort (master and target). These types of
  47. * errors occur during a config cycle where there is no device, like during
  48. * the discovery stage.
  49. */
  50. static int iop3xx_pci_status(void)
  51. {
  52. unsigned int status;
  53. int ret = 0;
  54. /*
  55. * Check the status registers.
  56. */
  57. status = *IOP3XX_ATUSR;
  58. if (status & 0xf900) {
  59. DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
  60. *IOP3XX_ATUSR = status & 0xf900;
  61. ret = 1;
  62. }
  63. status = *IOP3XX_ATUISR;
  64. if (status & 0x679f) {
  65. DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
  66. *IOP3XX_ATUISR = status & 0x679f;
  67. ret = 1;
  68. }
  69. return ret;
  70. }
  71. /*
  72. * Simply write the address register and read the configuration
  73. * data. Note that the 4 nops ensure that we are able to handle
  74. * a delayed abort (in theory.)
  75. */
  76. static u32 iop3xx_read(unsigned long addr)
  77. {
  78. u32 val;
  79. __asm__ __volatile__(
  80. "str %1, [%2]\n\t"
  81. "ldr %0, [%3]\n\t"
  82. "nop\n\t"
  83. "nop\n\t"
  84. "nop\n\t"
  85. "nop\n\t"
  86. : "=r" (val)
  87. : "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
  88. return val;
  89. }
  90. /*
  91. * The read routines must check the error status of the last configuration
  92. * cycle. If there was an error, the routine returns all hex f's.
  93. */
  94. static int
  95. iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where,
  96. int size, u32 *value)
  97. {
  98. unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
  99. u32 val = iop3xx_read(addr) >> ((where & 3) * 8);
  100. if (iop3xx_pci_status())
  101. val = 0xffffffff;
  102. *value = val;
  103. return PCIBIOS_SUCCESSFUL;
  104. }
  105. static int
  106. iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where,
  107. int size, u32 value)
  108. {
  109. unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
  110. u32 val;
  111. if (size != 4) {
  112. val = iop3xx_read(addr);
  113. if (iop3xx_pci_status())
  114. return PCIBIOS_SUCCESSFUL;
  115. where = (where & 3) * 8;
  116. if (size == 1)
  117. val &= ~(0xff << where);
  118. else
  119. val &= ~(0xffff << where);
  120. *IOP3XX_OCCDR = val | value << where;
  121. } else {
  122. asm volatile(
  123. "str %1, [%2]\n\t"
  124. "str %0, [%3]\n\t"
  125. "nop\n\t"
  126. "nop\n\t"
  127. "nop\n\t"
  128. "nop\n\t"
  129. :
  130. : "r" (value), "r" (addr),
  131. "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
  132. }
  133. return PCIBIOS_SUCCESSFUL;
  134. }
  135. struct pci_ops iop3xx_ops = {
  136. .read = iop3xx_read_config,
  137. .write = iop3xx_write_config,
  138. };
  139. /*
  140. * When a PCI device does not exist during config cycles, the 80200 gets a
  141. * bus error instead of returning 0xffffffff. This handler simply returns.
  142. */
  143. static int
  144. iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
  145. {
  146. DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
  147. addr, fsr, regs->ARM_pc, regs->ARM_lr);
  148. /*
  149. * If it was an imprecise abort, then we need to correct the
  150. * return address to be _after_ the instruction.
  151. */
  152. if (fsr & (1 << 10))
  153. regs->ARM_pc += 4;
  154. return 0;
  155. }
  156. int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
  157. {
  158. struct resource *res;
  159. struct resource realio;
  160. if (nr != 0)
  161. return 0;
  162. res = kzalloc(sizeof(struct resource), GFP_KERNEL);
  163. if (!res)
  164. panic("PCI: unable to alloc resources");
  165. res->start = IOP3XX_PCI_LOWER_MEM_PA;
  166. res->end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
  167. res->name = "IOP3XX PCI Memory Space";
  168. res->flags = IORESOURCE_MEM;
  169. request_resource(&iomem_resource, res);
  170. /*
  171. * Use whatever translation is already setup.
  172. */
  173. sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0;
  174. pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
  175. realio.start = 0;
  176. realio.end = realio.start + SZ_64K - 1;
  177. pci_remap_iospace(&realio, IOP3XX_PCI_LOWER_IO_PA);
  178. return 1;
  179. }
  180. void __init iop3xx_atu_setup(void)
  181. {
  182. /* BAR 0 ( Disabled ) */
  183. *IOP3XX_IAUBAR0 = 0x0;
  184. *IOP3XX_IABAR0 = 0x0;
  185. *IOP3XX_IATVR0 = 0x0;
  186. *IOP3XX_IALR0 = 0x0;
  187. /* BAR 1 ( Disabled ) */
  188. *IOP3XX_IAUBAR1 = 0x0;
  189. *IOP3XX_IABAR1 = 0x0;
  190. *IOP3XX_IALR1 = 0x0;
  191. /* BAR 2 (1:1 mapping with Physical RAM) */
  192. /* Set limit and enable */
  193. *IOP3XX_IALR2 = ~((u32)IOP3XX_MAX_RAM_SIZE - 1) & ~0x1;
  194. *IOP3XX_IAUBAR2 = 0x0;
  195. /* Align the inbound bar with the base of memory */
  196. *IOP3XX_IABAR2 = PHYS_OFFSET |
  197. PCI_BASE_ADDRESS_MEM_TYPE_64 |
  198. PCI_BASE_ADDRESS_MEM_PREFETCH;
  199. *IOP3XX_IATVR2 = PHYS_OFFSET;
  200. /* Outbound window 0 */
  201. *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA;
  202. *IOP3XX_OUMWTVR0 = 0;
  203. /* Outbound window 1 */
  204. *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA +
  205. IOP3XX_PCI_MEM_WINDOW_SIZE / 2;
  206. *IOP3XX_OUMWTVR1 = 0;
  207. /* BAR 3 ( Disabled ) */
  208. *IOP3XX_IAUBAR3 = 0x0;
  209. *IOP3XX_IABAR3 = 0x0;
  210. *IOP3XX_IATVR3 = 0x0;
  211. *IOP3XX_IALR3 = 0x0;
  212. /* Setup the I/O Bar
  213. */
  214. *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA;
  215. /* Enable inbound and outbound cycles
  216. */
  217. *IOP3XX_ATUCMD |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  218. PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  219. *IOP3XX_ATUCR |= IOP3XX_ATUCR_OUT_EN;
  220. }
  221. void __init iop3xx_atu_disable(void)
  222. {
  223. *IOP3XX_ATUCMD = 0;
  224. *IOP3XX_ATUCR = 0;
  225. /* wait for cycles to quiesce */
  226. while (*IOP3XX_PCSR & (IOP3XX_PCSR_OUT_Q_BUSY |
  227. IOP3XX_PCSR_IN_Q_BUSY))
  228. cpu_relax();
  229. /* BAR 0 ( Disabled ) */
  230. *IOP3XX_IAUBAR0 = 0x0;
  231. *IOP3XX_IABAR0 = 0x0;
  232. *IOP3XX_IATVR0 = 0x0;
  233. *IOP3XX_IALR0 = 0x0;
  234. /* BAR 1 ( Disabled ) */
  235. *IOP3XX_IAUBAR1 = 0x0;
  236. *IOP3XX_IABAR1 = 0x0;
  237. *IOP3XX_IALR1 = 0x0;
  238. /* BAR 2 ( Disabled ) */
  239. *IOP3XX_IAUBAR2 = 0x0;
  240. *IOP3XX_IABAR2 = 0x0;
  241. *IOP3XX_IATVR2 = 0x0;
  242. *IOP3XX_IALR2 = 0x0;
  243. /* BAR 3 ( Disabled ) */
  244. *IOP3XX_IAUBAR3 = 0x0;
  245. *IOP3XX_IABAR3 = 0x0;
  246. *IOP3XX_IATVR3 = 0x0;
  247. *IOP3XX_IALR3 = 0x0;
  248. /* Clear the outbound windows */
  249. *IOP3XX_OIOWTVR = 0;
  250. /* Outbound window 0 */
  251. *IOP3XX_OMWTVR0 = 0;
  252. *IOP3XX_OUMWTVR0 = 0;
  253. /* Outbound window 1 */
  254. *IOP3XX_OMWTVR1 = 0;
  255. *IOP3XX_OUMWTVR1 = 0;
  256. }
  257. /* Flag to determine whether the ATU is initialized and the PCI bus scanned */
  258. int init_atu;
  259. int iop3xx_get_init_atu(void) {
  260. /* check if default has been overridden */
  261. if (init_atu != IOP3XX_INIT_ATU_DEFAULT)
  262. return init_atu;
  263. else
  264. return IOP3XX_INIT_ATU_DISABLE;
  265. }
  266. static void __init iop3xx_atu_debug(void)
  267. {
  268. DBG("PCI: Intel IOP3xx PCI init.\n");
  269. DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n",
  270. *IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0);
  271. DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n",
  272. *IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1);
  273. DBG("PCI: Outbound IO window: PCI 0x%08x\n",
  274. *IOP3XX_OIOWTVR);
  275. DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
  276. *IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
  277. DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n",
  278. *IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1);
  279. DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
  280. *IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
  281. DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
  282. *IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
  283. DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
  284. 0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
  285. DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
  286. DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
  287. hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, 0, "imprecise external abort");
  288. }
  289. /* for platforms that might be host-bus-adapters */
  290. void __init iop3xx_pci_preinit_cond(void)
  291. {
  292. if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
  293. iop3xx_atu_disable();
  294. iop3xx_atu_setup();
  295. iop3xx_atu_debug();
  296. }
  297. }
  298. void __init iop3xx_pci_preinit(void)
  299. {
  300. pcibios_min_mem = 0;
  301. iop3xx_atu_disable();
  302. iop3xx_atu_setup();
  303. iop3xx_atu_debug();
  304. }
  305. /* allow init_atu to be user overridden */
  306. static int __init iop3xx_init_atu_setup(char *str)
  307. {
  308. init_atu = IOP3XX_INIT_ATU_DEFAULT;
  309. if (str) {
  310. while (*str != '\0') {
  311. switch (*str) {
  312. case 'y':
  313. case 'Y':
  314. init_atu = IOP3XX_INIT_ATU_ENABLE;
  315. break;
  316. case 'n':
  317. case 'N':
  318. init_atu = IOP3XX_INIT_ATU_DISABLE;
  319. break;
  320. case ',':
  321. case '=':
  322. break;
  323. default:
  324. printk(KERN_DEBUG "\"%s\" malformed at "
  325. "character: \'%c\'",
  326. __func__,
  327. *str);
  328. *(str + 1) = '\0';
  329. }
  330. str++;
  331. }
  332. }
  333. return 1;
  334. }
  335. __setup("iop3xx_init_atu", iop3xx_init_atu_setup);