tzic.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  4. */
  5. #include <linux/init.h>
  6. #include <linux/device.h>
  7. #include <linux/errno.h>
  8. #include <linux/io.h>
  9. #include <linux/irqchip.h>
  10. #include <linux/irqdomain.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include <asm/mach/irq.h>
  14. #include <asm/exception.h>
  15. #include "common.h"
  16. #include "hardware.h"
  17. #include "irq-common.h"
  18. /*
  19. *****************************************
  20. * TZIC Registers *
  21. *****************************************
  22. */
  23. #define TZIC_INTCNTL 0x0000 /* Control register */
  24. #define TZIC_INTTYPE 0x0004 /* Controller Type register */
  25. #define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
  26. #define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
  27. #define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
  28. #define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
  29. #define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
  30. #define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
  31. #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
  32. #define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
  33. #define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */
  34. #define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */
  35. #define TZIC_PND0 0x0D00 /* Pending Register 0 */
  36. #define TZIC_HIPND(i) (0x0D80+ ((i) << 2)) /* High Priority Pending Register */
  37. #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */
  38. #define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
  39. #define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
  40. static void __iomem *tzic_base;
  41. static struct irq_domain *domain;
  42. #define TZIC_NUM_IRQS 128
  43. #ifdef CONFIG_FIQ
  44. static int tzic_set_irq_fiq(unsigned int hwirq, unsigned int type)
  45. {
  46. unsigned int index, mask, value;
  47. index = hwirq >> 5;
  48. if (unlikely(index >= 4))
  49. return -EINVAL;
  50. mask = 1U << (hwirq & 0x1F);
  51. value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
  52. if (type)
  53. value &= ~mask;
  54. imx_writel(value, tzic_base + TZIC_INTSEC0(index));
  55. return 0;
  56. }
  57. #else
  58. #define tzic_set_irq_fiq NULL
  59. #endif
  60. #ifdef CONFIG_PM
  61. static void tzic_irq_suspend(struct irq_data *d)
  62. {
  63. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  64. int idx = d->hwirq >> 5;
  65. imx_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
  66. }
  67. static void tzic_irq_resume(struct irq_data *d)
  68. {
  69. int idx = d->hwirq >> 5;
  70. imx_writel(imx_readl(tzic_base + TZIC_ENSET0(idx)),
  71. tzic_base + TZIC_WAKEUP0(idx));
  72. }
  73. #else
  74. #define tzic_irq_suspend NULL
  75. #define tzic_irq_resume NULL
  76. #endif
  77. static struct mxc_extra_irq tzic_extra_irq = {
  78. #ifdef CONFIG_FIQ
  79. .set_irq_fiq = tzic_set_irq_fiq,
  80. #endif
  81. };
  82. static __init void tzic_init_gc(int idx, unsigned int irq_start)
  83. {
  84. struct irq_chip_generic *gc;
  85. struct irq_chip_type *ct;
  86. gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
  87. handle_level_irq);
  88. gc->private = &tzic_extra_irq;
  89. gc->wake_enabled = IRQ_MSK(32);
  90. ct = gc->chip_types;
  91. ct->chip.irq_mask = irq_gc_mask_disable_reg;
  92. ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
  93. ct->chip.irq_set_wake = irq_gc_set_wake;
  94. ct->chip.irq_suspend = tzic_irq_suspend;
  95. ct->chip.irq_resume = tzic_irq_resume;
  96. ct->regs.disable = TZIC_ENCLEAR0(idx);
  97. ct->regs.enable = TZIC_ENSET0(idx);
  98. irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
  99. }
  100. static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
  101. {
  102. u32 stat;
  103. int i, irqofs, handled;
  104. do {
  105. handled = 0;
  106. for (i = 0; i < 4; i++) {
  107. stat = imx_readl(tzic_base + TZIC_HIPND(i)) &
  108. imx_readl(tzic_base + TZIC_INTSEC0(i));
  109. while (stat) {
  110. handled = 1;
  111. irqofs = fls(stat) - 1;
  112. generic_handle_domain_irq(domain, irqofs + i * 32);
  113. stat &= ~(1 << irqofs);
  114. }
  115. }
  116. } while (handled);
  117. }
  118. /*
  119. * This function initializes the TZIC hardware and disables all the
  120. * interrupts. It registers the interrupt enable and disable functions
  121. * to the kernel for each interrupt source.
  122. */
  123. static int __init tzic_init_dt(struct device_node *np, struct device_node *p)
  124. {
  125. int irq_base;
  126. int i;
  127. tzic_base = of_iomap(np, 0);
  128. WARN_ON(!tzic_base);
  129. /* put the TZIC into the reset value with
  130. * all interrupts disabled
  131. */
  132. i = imx_readl(tzic_base + TZIC_INTCNTL);
  133. imx_writel(0x80010001, tzic_base + TZIC_INTCNTL);
  134. imx_writel(0x1f, tzic_base + TZIC_PRIOMASK);
  135. imx_writel(0x02, tzic_base + TZIC_SYNCCTRL);
  136. for (i = 0; i < 4; i++)
  137. imx_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
  138. /* disable all interrupts */
  139. for (i = 0; i < 4; i++)
  140. imx_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
  141. /* all IRQ no FIQ Warning :: No selection */
  142. irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
  143. WARN_ON(irq_base < 0);
  144. domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
  145. &irq_domain_simple_ops, NULL);
  146. WARN_ON(!domain);
  147. for (i = 0; i < 4; i++, irq_base += 32)
  148. tzic_init_gc(i, irq_base);
  149. set_handle_irq(tzic_handle_irq);
  150. #ifdef CONFIG_FIQ
  151. /* Initialize FIQ */
  152. init_FIQ(FIQ_START);
  153. #endif
  154. pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
  155. return 0;
  156. }
  157. IRQCHIP_DECLARE(tzic, "fsl,tzic", tzic_init_dt);
  158. /**
  159. * tzic_enable_wake() - enable wakeup interrupt
  160. *
  161. * @return 0 if successful; non-zero otherwise
  162. *
  163. * This function provides an interrupt synchronization point that is required
  164. * by tzic enabled platforms before entering imx specific low power modes (ie,
  165. * those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode).
  166. */
  167. int tzic_enable_wake(void)
  168. {
  169. unsigned int i;
  170. imx_writel(1, tzic_base + TZIC_DSMINT);
  171. if (unlikely(imx_readl(tzic_base + TZIC_DSMINT) == 0))
  172. return -EAGAIN;
  173. for (i = 0; i < 4; i++)
  174. imx_writel(imx_readl(tzic_base + TZIC_ENSET0(i)),
  175. tzic_base + TZIC_WAKEUP0(i));
  176. return 0;
  177. }