system.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 1999 ARM Limited
  4. * Copyright (C) 2000 Deep Blue Solutions Ltd
  5. * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  6. * Copyright 2008 Juergen Beisert, [email protected]
  7. * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, [email protected]
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/clk.h>
  11. #include <linux/io.h>
  12. #include <linux/err.h>
  13. #include <linux/delay.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <asm/system_misc.h>
  17. #include <asm/proc-fns.h>
  18. #include <asm/mach-types.h>
  19. #include <asm/hardware/cache-l2x0.h>
  20. #include "common.h"
  21. #include "hardware.h"
  22. static void __iomem *wdog_base;
  23. static struct clk *wdog_clk;
  24. static int wcr_enable = (1 << 2);
  25. /*
  26. * Reset the system. It is called by machine_restart().
  27. */
  28. void mxc_restart(enum reboot_mode mode, const char *cmd)
  29. {
  30. if (!wdog_base)
  31. goto reset_fallback;
  32. if (!IS_ERR(wdog_clk))
  33. clk_enable(wdog_clk);
  34. /* Assert SRS signal */
  35. imx_writew(wcr_enable, wdog_base);
  36. /*
  37. * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
  38. * written twice), we add another two writes to ensure there must be at
  39. * least two writes happen in the same one 32kHz clock period. We save
  40. * the target check here, since the writes shouldn't be a huge burden
  41. * for other platforms.
  42. */
  43. imx_writew(wcr_enable, wdog_base);
  44. imx_writew(wcr_enable, wdog_base);
  45. /* wait for reset to assert... */
  46. mdelay(500);
  47. pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
  48. /* delay to allow the serial port to show the message */
  49. mdelay(50);
  50. reset_fallback:
  51. /* we'll take a jump through zero as a poor second */
  52. soft_restart(0);
  53. }
  54. void __init mxc_arch_reset_init(void __iomem *base)
  55. {
  56. wdog_base = base;
  57. wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
  58. if (IS_ERR(wdog_clk))
  59. pr_warn("%s: failed to get wdog clock\n", __func__);
  60. else
  61. clk_prepare(wdog_clk);
  62. }
  63. #ifdef CONFIG_SOC_IMX1
  64. void __init imx1_reset_init(void __iomem *base)
  65. {
  66. wcr_enable = (1 << 0);
  67. mxc_arch_reset_init(base);
  68. }
  69. #endif
  70. #ifdef CONFIG_CACHE_L2X0
  71. void __init imx_init_l2cache(void)
  72. {
  73. void __iomem *l2x0_base;
  74. struct device_node *np;
  75. unsigned int val;
  76. np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
  77. if (!np)
  78. return;
  79. l2x0_base = of_iomap(np, 0);
  80. if (!l2x0_base)
  81. goto put_node;
  82. if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
  83. /* Configure the L2 PREFETCH and POWER registers */
  84. val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
  85. val |= L310_PREFETCH_CTRL_DBL_LINEFILL |
  86. L310_PREFETCH_CTRL_INSTR_PREFETCH |
  87. L310_PREFETCH_CTRL_DATA_PREFETCH;
  88. /* Set perfetch offset to improve performance */
  89. val &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
  90. val |= 15;
  91. writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
  92. }
  93. iounmap(l2x0_base);
  94. put_node:
  95. of_node_put(np);
  96. }
  97. #endif