avic.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  4. * Copyright 2008 Juergen Beisert, [email protected]
  5. */
  6. #include <linux/module.h>
  7. #include <linux/irq.h>
  8. #include <linux/irqdomain.h>
  9. #include <linux/irqchip.h>
  10. #include <linux/io.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include <asm/mach/irq.h>
  14. #include <asm/exception.h>
  15. #include "common.h"
  16. #include "hardware.h"
  17. #include "irq-common.h"
  18. #define AVIC_INTCNTL 0x00 /* int control reg */
  19. #define AVIC_NIMASK 0x04 /* int mask reg */
  20. #define AVIC_INTENNUM 0x08 /* int enable number reg */
  21. #define AVIC_INTDISNUM 0x0C /* int disable number reg */
  22. #define AVIC_INTENABLEH 0x10 /* int enable reg high */
  23. #define AVIC_INTENABLEL 0x14 /* int enable reg low */
  24. #define AVIC_INTTYPEH 0x18 /* int type reg high */
  25. #define AVIC_INTTYPEL 0x1C /* int type reg low */
  26. #define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */
  27. #define AVIC_NIVECSR 0x40 /* norm int vector/status */
  28. #define AVIC_FIVECSR 0x44 /* fast int vector/status */
  29. #define AVIC_INTSRCH 0x48 /* int source reg high */
  30. #define AVIC_INTSRCL 0x4C /* int source reg low */
  31. #define AVIC_INTFRCH 0x50 /* int force reg high */
  32. #define AVIC_INTFRCL 0x54 /* int force reg low */
  33. #define AVIC_NIPNDH 0x58 /* norm int pending high */
  34. #define AVIC_NIPNDL 0x5C /* norm int pending low */
  35. #define AVIC_FIPNDH 0x60 /* fast int pending high */
  36. #define AVIC_FIPNDL 0x64 /* fast int pending low */
  37. #define AVIC_NUM_IRQS 64
  38. /* low power interrupt mask registers */
  39. #define MX25_CCM_LPIMR0 0x68
  40. #define MX25_CCM_LPIMR1 0x6C
  41. static void __iomem *avic_base;
  42. static void __iomem *mx25_ccm_base;
  43. static struct irq_domain *domain;
  44. #ifdef CONFIG_FIQ
  45. static int avic_set_irq_fiq(unsigned int hwirq, unsigned int type)
  46. {
  47. unsigned int irqt;
  48. if (hwirq >= AVIC_NUM_IRQS)
  49. return -EINVAL;
  50. if (hwirq < AVIC_NUM_IRQS / 2) {
  51. irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq);
  52. imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL);
  53. } else {
  54. hwirq -= AVIC_NUM_IRQS / 2;
  55. irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq);
  56. imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH);
  57. }
  58. return 0;
  59. }
  60. #endif /* CONFIG_FIQ */
  61. static struct mxc_extra_irq avic_extra_irq = {
  62. #ifdef CONFIG_FIQ
  63. .set_irq_fiq = avic_set_irq_fiq,
  64. #endif
  65. };
  66. #ifdef CONFIG_PM
  67. static u32 avic_saved_mask_reg[2];
  68. static void avic_irq_suspend(struct irq_data *d)
  69. {
  70. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  71. struct irq_chip_type *ct = gc->chip_types;
  72. int idx = d->hwirq >> 5;
  73. avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask);
  74. imx_writel(gc->wake_active, avic_base + ct->regs.mask);
  75. if (mx25_ccm_base) {
  76. u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?
  77. MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;
  78. /*
  79. * The interrupts which are still enabled will be used as wakeup
  80. * sources. Allow those interrupts in low-power mode.
  81. * The LPIMR registers use 0 to allow an interrupt, the AVIC
  82. * registers use 1.
  83. */
  84. imx_writel(~gc->wake_active, mx25_ccm_base + offs);
  85. }
  86. }
  87. static void avic_irq_resume(struct irq_data *d)
  88. {
  89. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  90. struct irq_chip_type *ct = gc->chip_types;
  91. int idx = d->hwirq >> 5;
  92. imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
  93. if (mx25_ccm_base) {
  94. u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?
  95. MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;
  96. imx_writel(0xffffffff, mx25_ccm_base + offs);
  97. }
  98. }
  99. #else
  100. #define avic_irq_suspend NULL
  101. #define avic_irq_resume NULL
  102. #endif
  103. static __init void avic_init_gc(int idx, unsigned int irq_start)
  104. {
  105. struct irq_chip_generic *gc;
  106. struct irq_chip_type *ct;
  107. gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
  108. handle_level_irq);
  109. gc->private = &avic_extra_irq;
  110. gc->wake_enabled = IRQ_MSK(32);
  111. ct = gc->chip_types;
  112. ct->chip.irq_mask = irq_gc_mask_clr_bit;
  113. ct->chip.irq_unmask = irq_gc_mask_set_bit;
  114. ct->chip.irq_ack = irq_gc_mask_clr_bit;
  115. ct->chip.irq_set_wake = irq_gc_set_wake;
  116. ct->chip.irq_suspend = avic_irq_suspend;
  117. ct->chip.irq_resume = avic_irq_resume;
  118. ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
  119. ct->regs.ack = ct->regs.mask;
  120. irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
  121. }
  122. static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
  123. {
  124. u32 nivector;
  125. do {
  126. nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16;
  127. if (nivector == 0xffff)
  128. break;
  129. generic_handle_domain_irq(domain, nivector);
  130. } while (1);
  131. }
  132. /*
  133. * This function initializes the AVIC hardware and disables all the
  134. * interrupts. It registers the interrupt enable and disable functions
  135. * to the kernel for each interrupt source.
  136. */
  137. static void __init mxc_init_irq(void __iomem *irqbase)
  138. {
  139. struct device_node *np;
  140. int irq_base;
  141. int i;
  142. avic_base = irqbase;
  143. np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
  144. mx25_ccm_base = of_iomap(np, 0);
  145. if (mx25_ccm_base) {
  146. /*
  147. * By default, we mask all interrupts. We set the actual mask
  148. * before we go into low-power mode.
  149. */
  150. imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR0);
  151. imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR1);
  152. }
  153. /* put the AVIC into the reset value with
  154. * all interrupts disabled
  155. */
  156. imx_writel(0, avic_base + AVIC_INTCNTL);
  157. imx_writel(0x1f, avic_base + AVIC_NIMASK);
  158. /* disable all interrupts */
  159. imx_writel(0, avic_base + AVIC_INTENABLEH);
  160. imx_writel(0, avic_base + AVIC_INTENABLEL);
  161. /* all IRQ no FIQ */
  162. imx_writel(0, avic_base + AVIC_INTTYPEH);
  163. imx_writel(0, avic_base + AVIC_INTTYPEL);
  164. irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
  165. WARN_ON(irq_base < 0);
  166. np = of_find_compatible_node(NULL, NULL, "fsl,avic");
  167. domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
  168. &irq_domain_simple_ops, NULL);
  169. WARN_ON(!domain);
  170. for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
  171. avic_init_gc(i, irq_base);
  172. /* Set default priority value (0) for all IRQ's */
  173. for (i = 0; i < 8; i++)
  174. imx_writel(0, avic_base + AVIC_NIPRIORITY(i));
  175. set_handle_irq(avic_handle_irq);
  176. #ifdef CONFIG_FIQ
  177. /* Initialize FIQ */
  178. init_FIQ(FIQ_START);
  179. #endif
  180. printk(KERN_INFO "MXC IRQ initialized\n");
  181. }
  182. static int __init imx_avic_init(struct device_node *node,
  183. struct device_node *parent)
  184. {
  185. void __iomem *avic_base;
  186. avic_base = of_iomap(node, 0);
  187. BUG_ON(!avic_base);
  188. mxc_init_irq(avic_base);
  189. return 0;
  190. }
  191. IRQCHIP_DECLARE(imx_avic, "fsl,avic", imx_avic_init);