anatop.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
  4. * Copyright 2017-2018 NXP.
  5. */
  6. #include <linux/err.h>
  7. #include <linux/io.h>
  8. #include <linux/of.h>
  9. #include <linux/of_address.h>
  10. #include <linux/mfd/syscon.h>
  11. #include <linux/regmap.h>
  12. #include "common.h"
  13. #include "hardware.h"
  14. #define REG_SET 0x4
  15. #define REG_CLR 0x8
  16. #define ANADIG_REG_2P5 0x130
  17. #define ANADIG_REG_CORE 0x140
  18. #define ANADIG_ANA_MISC0 0x150
  19. #define ANADIG_DIGPROG 0x260
  20. #define ANADIG_DIGPROG_IMX6SL 0x280
  21. #define ANADIG_DIGPROG_IMX7D 0x800
  22. #define SRC_SBMR2 0x1c
  23. #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
  24. #define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8
  25. #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
  26. #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
  27. /* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
  28. #define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
  29. static struct regmap *anatop;
  30. static void imx_anatop_enable_weak2p5(bool enable)
  31. {
  32. u32 reg, val;
  33. regmap_read(anatop, ANADIG_ANA_MISC0, &val);
  34. /* can only be enabled when stop_mode_config is clear. */
  35. reg = ANADIG_REG_2P5;
  36. reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ?
  37. REG_SET : REG_CLR;
  38. regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG);
  39. }
  40. static void imx_anatop_enable_fet_odrive(bool enable)
  41. {
  42. regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR),
  43. BM_ANADIG_REG_CORE_FET_ODRIVE);
  44. }
  45. static inline void imx_anatop_enable_2p5_pulldown(bool enable)
  46. {
  47. regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),
  48. BM_ANADIG_REG_2P5_ENABLE_PULLDOWN);
  49. }
  50. static inline void imx_anatop_disconnect_high_snvs(bool enable)
  51. {
  52. regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),
  53. BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS);
  54. }
  55. void imx_anatop_pre_suspend(void)
  56. {
  57. if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
  58. imx_anatop_enable_2p5_pulldown(true);
  59. else
  60. imx_anatop_enable_weak2p5(true);
  61. imx_anatop_enable_fet_odrive(true);
  62. if (cpu_is_imx6sl())
  63. imx_anatop_disconnect_high_snvs(true);
  64. }
  65. void imx_anatop_post_resume(void)
  66. {
  67. if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
  68. imx_anatop_enable_2p5_pulldown(false);
  69. else
  70. imx_anatop_enable_weak2p5(false);
  71. imx_anatop_enable_fet_odrive(false);
  72. if (cpu_is_imx6sl())
  73. imx_anatop_disconnect_high_snvs(false);
  74. }
  75. void __init imx_init_revision_from_anatop(void)
  76. {
  77. struct device_node *np, *src_np;
  78. void __iomem *anatop_base;
  79. unsigned int revision;
  80. u32 digprog;
  81. u16 offset = ANADIG_DIGPROG;
  82. u8 major_part, minor_part;
  83. np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
  84. anatop_base = of_iomap(np, 0);
  85. WARN_ON(!anatop_base);
  86. if (of_device_is_compatible(np, "fsl,imx6sl-anatop"))
  87. offset = ANADIG_DIGPROG_IMX6SL;
  88. if (of_device_is_compatible(np, "fsl,imx7d-anatop"))
  89. offset = ANADIG_DIGPROG_IMX7D;
  90. digprog = readl_relaxed(anatop_base + offset);
  91. iounmap(anatop_base);
  92. /*
  93. * On i.MX7D digprog value match linux version format, so
  94. * it needn't map again and we can use register value directly.
  95. */
  96. if (of_device_is_compatible(np, "fsl,imx7d-anatop")) {
  97. revision = digprog & 0xff;
  98. } else {
  99. /*
  100. * MAJOR: [15:8], the major silicon revison;
  101. * MINOR: [7: 0], the minor silicon revison;
  102. *
  103. * please refer to the i.MX RM for the detailed
  104. * silicon revison bit define.
  105. * format the major part and minor part to match the
  106. * linux kernel soc version format.
  107. */
  108. major_part = (digprog >> 8) & 0xf;
  109. minor_part = digprog & 0xf;
  110. revision = ((major_part + 1) << 4) | minor_part;
  111. if ((digprog >> 16) == MXC_CPU_IMX6ULL) {
  112. void __iomem *src_base;
  113. u32 sbmr2;
  114. src_np = of_find_compatible_node(NULL, NULL,
  115. "fsl,imx6ul-src");
  116. src_base = of_iomap(src_np, 0);
  117. of_node_put(src_np);
  118. WARN_ON(!src_base);
  119. sbmr2 = readl_relaxed(src_base + SRC_SBMR2);
  120. iounmap(src_base);
  121. /* src_sbmr2 bit 6 is to identify if it is i.MX6ULZ */
  122. if (sbmr2 & (1 << 6)) {
  123. digprog &= ~(0xff << 16);
  124. digprog |= (MXC_CPU_IMX6ULZ << 16);
  125. }
  126. }
  127. }
  128. of_node_put(np);
  129. mxc_set_cpu_type(digprog >> 16 & 0xff);
  130. imx_set_soc_revision(revision);
  131. }
  132. void __init imx_anatop_init(void)
  133. {
  134. anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
  135. if (IS_ERR(anatop))
  136. pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
  137. }