soc.h 8.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212
  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * arch/arm/mach-ep93xx/soc.h
  4. *
  5. * Copyright (C) 2012 Open Kernel Labs <www.ok-labs.com>
  6. * Copyright (C) 2012 Ryan Mallon <[email protected]>
  7. */
  8. #ifndef _EP93XX_SOC_H
  9. #define _EP93XX_SOC_H
  10. #include "ep93xx-regs.h"
  11. #include "irqs.h"
  12. /*
  13. * EP93xx Physical Memory Map:
  14. *
  15. * The ASDO pin is sampled at system reset to select a synchronous or
  16. * asynchronous boot configuration. When ASDO is "1" (i.e. pulled-up)
  17. * the synchronous boot mode is selected. When ASDO is "0" (i.e
  18. * pulled-down) the asynchronous boot mode is selected.
  19. *
  20. * In synchronous boot mode nSDCE3 is decoded starting at physical address
  21. * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
  22. * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
  23. * decoded at 0xf0000000.
  24. *
  25. * There is known errata for the EP93xx dealing with External Memory
  26. * Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design
  27. * Guidelines" for more information. This document can be found at:
  28. *
  29. * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
  30. */
  31. #define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
  32. #define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
  33. #define EP93XX_CS1_PHYS_BASE 0x10000000
  34. #define EP93XX_CS2_PHYS_BASE 0x20000000
  35. #define EP93XX_CS3_PHYS_BASE 0x30000000
  36. #define EP93XX_PCMCIA_PHYS_BASE 0x40000000
  37. #define EP93XX_CS6_PHYS_BASE 0x60000000
  38. #define EP93XX_CS7_PHYS_BASE 0x70000000
  39. #define EP93XX_SDCE0_PHYS_BASE 0xc0000000
  40. #define EP93XX_SDCE1_PHYS_BASE 0xd0000000
  41. #define EP93XX_SDCE2_PHYS_BASE 0xe0000000
  42. #define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin = 0 */
  43. #define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin = 1 */
  44. /* AHB peripherals */
  45. #define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000)
  46. #define EP93XX_ETHERNET_PHYS_BASE EP93XX_AHB_PHYS(0x00010000)
  47. #define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000)
  48. #define EP93XX_USB_PHYS_BASE EP93XX_AHB_PHYS(0x00020000)
  49. #define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000)
  50. #define EP93XX_RASTER_PHYS_BASE EP93XX_AHB_PHYS(0x00030000)
  51. #define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000)
  52. #define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000)
  53. #define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000)
  54. #define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000)
  55. #define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000)
  56. #define EP93XX_IDE_PHYS_BASE EP93XX_AHB_PHYS(0x000a0000)
  57. #define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000)
  58. #define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000)
  59. #define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000)
  60. /* APB peripherals */
  61. #define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000)
  62. #define EP93XX_I2S_PHYS_BASE EP93XX_APB_PHYS(0x00020000)
  63. #define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
  64. #define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
  65. #define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000)
  66. #define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000)
  67. #define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000)
  68. #define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000)
  69. #define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000)
  70. #define EP93XX_KEY_MATRIX_PHYS_BASE EP93XX_APB_PHYS(0x000f0000)
  71. #define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000)
  72. #define EP93XX_ADC_PHYS_BASE EP93XX_APB_PHYS(0x00100000)
  73. #define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000)
  74. #define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000)
  75. #define EP93XX_PWM_PHYS_BASE EP93XX_APB_PHYS(0x00110000)
  76. #define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000)
  77. #define EP93XX_RTC_PHYS_BASE EP93XX_APB_PHYS(0x00120000)
  78. #define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000)
  79. #define EP93XX_WATCHDOG_PHYS_BASE EP93XX_APB_PHYS(0x00140000)
  80. #define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000)
  81. /* System controller */
  82. #define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000)
  83. #define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
  84. #define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
  85. #define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
  86. #define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
  87. #define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
  88. #define EP93XX_SYSCON_PWRCNT_USH_EN 28
  89. #define EP93XX_SYSCON_PWRCNT_DMA_M2M1 27
  90. #define EP93XX_SYSCON_PWRCNT_DMA_M2M0 26
  91. #define EP93XX_SYSCON_PWRCNT_DMA_M2P8 25
  92. #define EP93XX_SYSCON_PWRCNT_DMA_M2P9 24
  93. #define EP93XX_SYSCON_PWRCNT_DMA_M2P6 23
  94. #define EP93XX_SYSCON_PWRCNT_DMA_M2P7 22
  95. #define EP93XX_SYSCON_PWRCNT_DMA_M2P4 21
  96. #define EP93XX_SYSCON_PWRCNT_DMA_M2P5 20
  97. #define EP93XX_SYSCON_PWRCNT_DMA_M2P2 19
  98. #define EP93XX_SYSCON_PWRCNT_DMA_M2P3 18
  99. #define EP93XX_SYSCON_PWRCNT_DMA_M2P0 17
  100. #define EP93XX_SYSCON_PWRCNT_DMA_M2P1 16
  101. #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
  102. #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
  103. #define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
  104. #define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23)
  105. #define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24)
  106. #define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19)
  107. #define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18)
  108. #define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
  109. #define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
  110. #define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
  111. #define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
  112. #define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
  113. #define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
  114. #define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
  115. #define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
  116. #define EP93XX_SYSCON_DEVCFG_U3EN 24
  117. #define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
  118. #define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
  119. #define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
  120. #define EP93XX_SYSCON_DEVCFG_U2EN 20
  121. #define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
  122. #define EP93XX_SYSCON_DEVCFG_U1EN 18
  123. #define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
  124. #define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
  125. #define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
  126. #define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
  127. #define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
  128. #define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
  129. #define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
  130. #define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
  131. #define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
  132. #define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
  133. #define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
  134. #define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
  135. #define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
  136. #define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
  137. #define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
  138. #define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
  139. #define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
  140. #define EP93XX_SYSCON_CLKDIV_ENABLE 15
  141. #define EP93XX_SYSCON_CLKDIV_ESEL (1<<14)
  142. #define EP93XX_SYSCON_CLKDIV_PSEL (1<<13)
  143. #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
  144. #define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
  145. #define EP93XX_SYSCON_I2SCLKDIV_SENA 31
  146. #define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29)
  147. #define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19)
  148. #define EP93XX_I2SCLKDIV_SDIV (1 << 16)
  149. #define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17)
  150. #define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17)
  151. #define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17)
  152. #define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17)
  153. #define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
  154. #define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN 31
  155. #define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV 16
  156. #define EP93XX_SYSCON_KEYTCHCLKDIV_KEN 15
  157. #define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
  158. #define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
  159. #define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
  160. #define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28)
  161. #define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8)
  162. #define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7)
  163. #define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6)
  164. #define EP93XX_SYSCON_SYSCFG_LASDO (1<<5)
  165. #define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4)
  166. #define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3)
  167. #define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1)
  168. #define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
  169. #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
  170. /* EP93xx System Controller software locked register write */
  171. void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
  172. void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
  173. static inline void ep93xx_devcfg_set_bits(unsigned int bits)
  174. {
  175. ep93xx_devcfg_set_clear(bits, 0x00);
  176. }
  177. static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
  178. {
  179. ep93xx_devcfg_set_clear(0x00, bits);
  180. }
  181. #endif /* _EP93XX_SOC_H */