pm.h 2.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. #ifndef __ASM_ARCH_PM_H
  3. #define __ASM_ARCH_PM_H
  4. #include <asm/errno.h>
  5. #include "irqs.h"
  6. #define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
  7. #define CLOCK_GATING_BIT_USB0 0
  8. #define CLOCK_GATING_BIT_USB1 1
  9. #define CLOCK_GATING_BIT_GBE 2
  10. #define CLOCK_GATING_BIT_SATA 3
  11. #define CLOCK_GATING_BIT_PCIE0 4
  12. #define CLOCK_GATING_BIT_PCIE1 5
  13. #define CLOCK_GATING_BIT_SDIO0 8
  14. #define CLOCK_GATING_BIT_SDIO1 9
  15. #define CLOCK_GATING_BIT_NAND 10
  16. #define CLOCK_GATING_BIT_CAMERA 11
  17. #define CLOCK_GATING_BIT_I2S0 12
  18. #define CLOCK_GATING_BIT_I2S1 13
  19. #define CLOCK_GATING_BIT_CRYPTO 15
  20. #define CLOCK_GATING_BIT_AC97 21
  21. #define CLOCK_GATING_BIT_PDMA 22
  22. #define CLOCK_GATING_BIT_XOR0 23
  23. #define CLOCK_GATING_BIT_XOR1 24
  24. #define CLOCK_GATING_BIT_GIGA_PHY 30
  25. #define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0)
  26. #define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1)
  27. #define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE)
  28. #define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA)
  29. #define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0)
  30. #define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1)
  31. #define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0)
  32. #define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1)
  33. #define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND)
  34. #define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA)
  35. #define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0)
  36. #define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1)
  37. #define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO)
  38. #define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97)
  39. #define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA)
  40. #define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0)
  41. #define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1)
  42. #define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY)
  43. #define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
  44. #define PMU_SW_RST_VIDEO_MASK BIT(16)
  45. #define PMU_SW_RST_GPU_MASK BIT(18)
  46. #define PMU_PWR_GPU_PWR_DWN_MASK BIT(2)
  47. #define PMU_PWR_VPU_PWR_DWN_MASK BIT(3)
  48. #define PMU_ISO_VIDEO_MASK BIT(0)
  49. #define PMU_ISO_GPU_MASK BIT(1)
  50. #endif