pcie.c 5.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * arch/arm/mach-dove/pcie.c
  4. *
  5. * PCIe functions for Marvell Dove 88AP510 SoC
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/pci.h>
  9. #include <linux/clk.h>
  10. #include <video/vga.h>
  11. #include <asm/mach/pci.h>
  12. #include <asm/mach/arch.h>
  13. #include <asm/setup.h>
  14. #include <asm/delay.h>
  15. #include <plat/pcie.h>
  16. #include <plat/addr-map.h>
  17. #include "irqs.h"
  18. #include "bridge-regs.h"
  19. #include "common.h"
  20. struct pcie_port {
  21. u8 index;
  22. u8 root_bus_nr;
  23. void __iomem *base;
  24. spinlock_t conf_lock;
  25. char mem_space_name[16];
  26. struct resource res;
  27. };
  28. static struct pcie_port pcie_port[2];
  29. static int num_pcie_ports;
  30. static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
  31. {
  32. struct pcie_port *pp;
  33. struct resource realio;
  34. if (nr >= num_pcie_ports)
  35. return 0;
  36. pp = &pcie_port[nr];
  37. sys->private_data = pp;
  38. pp->root_bus_nr = sys->busnr;
  39. /*
  40. * Generic PCIe unit setup.
  41. */
  42. orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
  43. orion_pcie_setup(pp->base);
  44. realio.start = sys->busnr * SZ_64K;
  45. realio.end = realio.start + SZ_64K - 1;
  46. pci_remap_iospace(&realio, pp->index == 0 ? DOVE_PCIE0_IO_PHYS_BASE :
  47. DOVE_PCIE1_IO_PHYS_BASE);
  48. /*
  49. * IORESOURCE_MEM
  50. */
  51. snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
  52. "PCIe %d MEM", pp->index);
  53. pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
  54. pp->res.name = pp->mem_space_name;
  55. if (pp->index == 0) {
  56. pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
  57. pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
  58. } else {
  59. pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
  60. pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
  61. }
  62. pp->res.flags = IORESOURCE_MEM;
  63. if (request_resource(&iomem_resource, &pp->res))
  64. panic("Request PCIe Memory resource failed\n");
  65. pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
  66. return 1;
  67. }
  68. static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
  69. {
  70. /*
  71. * Don't go out when trying to access nonexisting devices
  72. * on the local bus.
  73. */
  74. if (bus == pp->root_bus_nr && dev > 1)
  75. return 0;
  76. return 1;
  77. }
  78. static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
  79. int size, u32 *val)
  80. {
  81. struct pci_sys_data *sys = bus->sysdata;
  82. struct pcie_port *pp = sys->private_data;
  83. unsigned long flags;
  84. int ret;
  85. if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
  86. *val = 0xffffffff;
  87. return PCIBIOS_DEVICE_NOT_FOUND;
  88. }
  89. spin_lock_irqsave(&pp->conf_lock, flags);
  90. ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
  91. spin_unlock_irqrestore(&pp->conf_lock, flags);
  92. return ret;
  93. }
  94. static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
  95. int where, int size, u32 val)
  96. {
  97. struct pci_sys_data *sys = bus->sysdata;
  98. struct pcie_port *pp = sys->private_data;
  99. unsigned long flags;
  100. int ret;
  101. if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
  102. return PCIBIOS_DEVICE_NOT_FOUND;
  103. spin_lock_irqsave(&pp->conf_lock, flags);
  104. ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
  105. spin_unlock_irqrestore(&pp->conf_lock, flags);
  106. return ret;
  107. }
  108. static struct pci_ops pcie_ops = {
  109. .read = pcie_rd_conf,
  110. .write = pcie_wr_conf,
  111. };
  112. /*
  113. * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
  114. * is operating as a root complex this needs to be switched to
  115. * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
  116. * the device. Decoding setup is handled by the orion code.
  117. */
  118. static void rc_pci_fixup(struct pci_dev *dev)
  119. {
  120. if (dev->bus->parent == NULL && dev->devfn == 0) {
  121. int i;
  122. dev->class &= 0xff;
  123. dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
  124. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  125. dev->resource[i].start = 0;
  126. dev->resource[i].end = 0;
  127. dev->resource[i].flags = 0;
  128. }
  129. }
  130. }
  131. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
  132. static int __init
  133. dove_pcie_scan_bus(int nr, struct pci_host_bridge *bridge)
  134. {
  135. struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
  136. if (nr >= num_pcie_ports) {
  137. BUG();
  138. return -EINVAL;
  139. }
  140. list_splice_init(&sys->resources, &bridge->windows);
  141. bridge->dev.parent = NULL;
  142. bridge->sysdata = sys;
  143. bridge->busnr = sys->busnr;
  144. bridge->ops = &pcie_ops;
  145. return pci_scan_root_bus_bridge(bridge);
  146. }
  147. static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  148. {
  149. struct pci_sys_data *sys = dev->sysdata;
  150. struct pcie_port *pp = sys->private_data;
  151. return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
  152. }
  153. static struct hw_pci dove_pci __initdata = {
  154. .nr_controllers = 2,
  155. .setup = dove_pcie_setup,
  156. .scan = dove_pcie_scan_bus,
  157. .map_irq = dove_pcie_map_irq,
  158. };
  159. static void __init add_pcie_port(int index, void __iomem *base)
  160. {
  161. printk(KERN_INFO "Dove PCIe port %d: ", index);
  162. if (orion_pcie_link_up(base)) {
  163. struct pcie_port *pp = &pcie_port[num_pcie_ports++];
  164. struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0"));
  165. if (!IS_ERR(clk))
  166. clk_prepare_enable(clk);
  167. printk(KERN_INFO "link up\n");
  168. pp->index = index;
  169. pp->root_bus_nr = -1;
  170. pp->base = base;
  171. spin_lock_init(&pp->conf_lock);
  172. memset(&pp->res, 0, sizeof(pp->res));
  173. } else {
  174. printk(KERN_INFO "link down, ignoring\n");
  175. }
  176. }
  177. void __init dove_pcie_init(int init_port0, int init_port1)
  178. {
  179. vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
  180. if (init_port0)
  181. add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
  182. if (init_port1)
  183. add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
  184. pci_common_init(&dove_pci);
  185. }