mpp.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * arch/arm/mach-dove/mpp.c
  4. *
  5. * MPP functions for Marvell Dove SoCs
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/gpio.h>
  9. #include <linux/io.h>
  10. #include <plat/mpp.h>
  11. #include <plat/orion-gpio.h>
  12. #include "dove.h"
  13. #include "mpp.h"
  14. struct dove_mpp_grp {
  15. int start;
  16. int end;
  17. };
  18. /* Map a group to a range of GPIO pins in that group */
  19. static const struct dove_mpp_grp dove_mpp_grp[] = {
  20. [MPP_24_39] = {
  21. .start = 24,
  22. .end = 39,
  23. },
  24. [MPP_40_45] = {
  25. .start = 40,
  26. .end = 45,
  27. },
  28. [MPP_46_51] = {
  29. .start = 46,
  30. .end = 51,
  31. },
  32. [MPP_58_61] = {
  33. .start = 58,
  34. .end = 61,
  35. },
  36. [MPP_62_63] = {
  37. .start = 62,
  38. .end = 63,
  39. },
  40. };
  41. /* Enable gpio for a range of pins. mode should be a combination of
  42. GPIO_OUTPUT_OK | GPIO_INPUT_OK */
  43. static void __init dove_mpp_gpio_mode(int start, int end, int gpio_mode)
  44. {
  45. int i;
  46. for (i = start; i <= end; i++)
  47. orion_gpio_set_valid(i, gpio_mode);
  48. }
  49. /* Dump all the extra MPP registers. The platform code will dump the
  50. registers for pins 0-23. */
  51. static void __init dove_mpp_dump_regs(void)
  52. {
  53. pr_debug("PMU_CTRL4_CTRL: %08x\n",
  54. readl(DOVE_MPP_CTRL4_VIRT_BASE));
  55. pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n",
  56. readl(DOVE_PMU_MPP_GENERAL_CTRL));
  57. pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
  58. }
  59. static void __init dove_mpp_cfg_nfc(int sel)
  60. {
  61. u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE);
  62. mpp_gen_cfg &= ~0x1;
  63. mpp_gen_cfg |= sel;
  64. writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE);
  65. dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK);
  66. }
  67. static void __init dove_mpp_cfg_au1(int sel)
  68. {
  69. u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
  70. u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
  71. u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
  72. u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
  73. mpp_ctrl4 &= ~(DOVE_AU1_GPIO_SEL);
  74. ssp_ctrl1 &= ~(DOVE_SSP_ON_AU1);
  75. mpp_gen_ctrl &= ~(DOVE_AU1_SPDIFO_GPIO_EN);
  76. global_cfg_2 &= ~(DOVE_TWSI_OPTION3_GPIO);
  77. if (!sel || sel == 0x2)
  78. dove_mpp_gpio_mode(52, 57, 0);
  79. else
  80. dove_mpp_gpio_mode(52, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
  81. if (sel & 0x1) {
  82. global_cfg_2 |= DOVE_TWSI_OPTION3_GPIO;
  83. dove_mpp_gpio_mode(56, 57, 0);
  84. }
  85. if (sel & 0x2) {
  86. mpp_gen_ctrl |= DOVE_AU1_SPDIFO_GPIO_EN;
  87. dove_mpp_gpio_mode(57, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
  88. }
  89. if (sel & 0x4) {
  90. ssp_ctrl1 |= DOVE_SSP_ON_AU1;
  91. dove_mpp_gpio_mode(52, 55, 0);
  92. }
  93. if (sel & 0x8)
  94. mpp_ctrl4 |= DOVE_AU1_GPIO_SEL;
  95. writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
  96. writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1);
  97. writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE);
  98. writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
  99. }
  100. /* Configure the group registers, enabling GPIO if sel indicates the
  101. pin is to be used for GPIO */
  102. static void __init dove_mpp_conf_grp(unsigned int *mpp_grp_list)
  103. {
  104. u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
  105. int gpio_mode;
  106. for ( ; *mpp_grp_list; mpp_grp_list++) {
  107. unsigned int num = MPP_NUM(*mpp_grp_list);
  108. unsigned int sel = MPP_SEL(*mpp_grp_list);
  109. if (num > MPP_GRP_MAX) {
  110. pr_err("dove: invalid MPP GRP number (%u)\n", num);
  111. continue;
  112. }
  113. mpp_ctrl4 &= ~(0x1 << num);
  114. mpp_ctrl4 |= sel << num;
  115. gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
  116. dove_mpp_gpio_mode(dove_mpp_grp[num].start,
  117. dove_mpp_grp[num].end, gpio_mode);
  118. }
  119. writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
  120. }
  121. /* Configure the various MPP pins on Dove */
  122. void __init dove_mpp_conf(unsigned int *mpp_list,
  123. unsigned int *mpp_grp_list,
  124. unsigned int grp_au1_52_57,
  125. unsigned int grp_nfc_64_71)
  126. {
  127. dove_mpp_dump_regs();
  128. /* Use platform code for pins 0-23 */
  129. orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE);
  130. dove_mpp_conf_grp(mpp_grp_list);
  131. dove_mpp_cfg_au1(grp_au1_52_57);
  132. dove_mpp_cfg_nfc(grp_nfc_64_71);
  133. dove_mpp_dump_regs();
  134. }