dove.h 6.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* Generic definitions for Marvell Dove 88AP510 SoC */
  3. #ifndef __ASM_ARCH_DOVE_H
  4. #define __ASM_ARCH_DOVE_H
  5. #include "irqs.h"
  6. /*
  7. * Marvell Dove address maps.
  8. *
  9. * phys virt size
  10. * c8000000 fdb00000 1M Cryptographic SRAM
  11. * e0000000 @runtime 128M PCIe-0 Memory space
  12. * e8000000 @runtime 128M PCIe-1 Memory space
  13. * f1000000 fec00000 1M on-chip south-bridge registers
  14. * f1800000 fe400000 8M on-chip north-bridge registers
  15. * f2000000 fee00000 1M PCIe-0 I/O space
  16. * f2100000 fef00000 1M PCIe-1 I/O space
  17. */
  18. #define DOVE_CESA_PHYS_BASE 0xc8000000
  19. #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
  20. #define DOVE_CESA_SIZE SZ_1M
  21. #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
  22. #define DOVE_PCIE0_MEM_SIZE SZ_128M
  23. #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
  24. #define DOVE_PCIE1_MEM_SIZE SZ_128M
  25. #define DOVE_BOOTROM_PHYS_BASE 0xf8000000
  26. #define DOVE_BOOTROM_SIZE SZ_128M
  27. #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
  28. #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
  29. #define DOVE_SCRATCHPAD_SIZE SZ_1M
  30. #define DOVE_SB_REGS_PHYS_BASE 0xf1000000
  31. #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfec00000)
  32. #define DOVE_SB_REGS_SIZE SZ_1M
  33. #define DOVE_NB_REGS_PHYS_BASE 0xf1800000
  34. #define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe400000)
  35. #define DOVE_NB_REGS_SIZE SZ_8M
  36. #define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
  37. #define DOVE_PCIE0_IO_BUS_BASE 0x00000000
  38. #define DOVE_PCIE0_IO_SIZE SZ_64K
  39. #define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000
  40. #define DOVE_PCIE1_IO_BUS_BASE 0x00010000
  41. #define DOVE_PCIE1_IO_SIZE SZ_64K
  42. /*
  43. * Dove Core Registers Map
  44. */
  45. /* SPI, I2C, UART */
  46. #define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000)
  47. #define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000)
  48. #define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000)
  49. #define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100)
  50. #define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100)
  51. #define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200)
  52. #define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200)
  53. #define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300)
  54. #define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300)
  55. #define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600)
  56. #define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600)
  57. /* North-South Bridge */
  58. #define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000)
  59. #define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000)
  60. #define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE)
  61. #define BRIDGE_WINS_SZ (0x80)
  62. /* Cryptographic Engine */
  63. #define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000)
  64. /* PCIe 0 */
  65. #define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000)
  66. /* USB */
  67. #define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000)
  68. #define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000)
  69. /* XOR 0 Engine */
  70. #define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800)
  71. #define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800)
  72. #define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00)
  73. #define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00)
  74. /* XOR 1 Engine */
  75. #define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900)
  76. #define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900)
  77. #define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00)
  78. #define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00)
  79. /* Gigabit Ethernet */
  80. #define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000)
  81. /* PCIe 1 */
  82. #define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000)
  83. /* CAFE */
  84. #define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000)
  85. #define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000)
  86. #define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000)
  87. #define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000)
  88. /* SATA */
  89. #define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000)
  90. /* I2S/SPDIF */
  91. #define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000)
  92. #define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000)
  93. /* NAND Flash Controller */
  94. #define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000)
  95. /* MPP, GPIO, Reset Sampling */
  96. #define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
  97. #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
  98. #define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014)
  99. #define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018)
  100. #define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
  101. #define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420)
  102. #define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
  103. #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
  104. #define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
  105. #define DOVE_NAND_GPIO_EN (1 << 0)
  106. #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
  107. #define DOVE_SPI_GPIO_SEL (1 << 5)
  108. #define DOVE_UART1_GPIO_SEL (1 << 4)
  109. #define DOVE_AU1_GPIO_SEL (1 << 3)
  110. #define DOVE_CAM_GPIO_SEL (1 << 2)
  111. #define DOVE_SD1_GPIO_SEL (1 << 1)
  112. #define DOVE_SD0_GPIO_SEL (1 << 0)
  113. /* Power Management */
  114. #define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000)
  115. #define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c)
  116. /* Real Time Clock */
  117. #define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500)
  118. /* AC97 */
  119. #define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000)
  120. #define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000)
  121. /* Peripheral DMA */
  122. #define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000)
  123. #define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000)
  124. #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
  125. #define DOVE_TWSI_ENABLE_OPTION1 (1 << 7)
  126. #define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
  127. #define DOVE_TWSI_ENABLE_OPTION2 (1 << 20)
  128. #define DOVE_TWSI_ENABLE_OPTION3 (1 << 21)
  129. #define DOVE_TWSI_OPTION3_GPIO (1 << 22)
  130. #define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000)
  131. #define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
  132. #define DOVE_SSP_ON_AU1 (1 << 0)
  133. #define DOVE_SSP_CLOCK_ENABLE (1 << 1)
  134. #define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)
  135. /* Memory Controller */
  136. #define DOVE_MC_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x00000)
  137. #define DOVE_MC_WINS_BASE (DOVE_MC_PHYS_BASE + 0x100)
  138. #define DOVE_MC_WINS_SZ (0x8)
  139. #define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000)
  140. /* LCD Controller */
  141. #define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
  142. #define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000)
  143. #define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
  144. #define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000)
  145. /* Graphic Engine */
  146. #define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000)
  147. /* Video Engine */
  148. #define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000)
  149. #endif