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mach-dove
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bridge-regs.h

bridge-regs.h 1.6 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /* Mbus-L to Mbus Bridge Registers */
    3. 

  3. 

  4. #ifndef __ASM_ARCH_BRIDGE_REGS_H
    5. 

  5. #define __ASM_ARCH_BRIDGE_REGS_H
    6. 

  6. 

  7. #include "dove.h"
    8. 

  8. 

  9. #define CPU_CONFIG		(BRIDGE_VIRT_BASE + 0x0000)
    10. 

  10. 

  11. #define CPU_CONTROL		(BRIDGE_VIRT_BASE + 0x0104)
    12. 

  12. #define  CPU_CTRL_PCIE0_LINK	0x00000001
    13. 

  13. #define  CPU_RESET		0x00000002
    14. 

  14. #define  CPU_CTRL_PCIE1_LINK	0x00000008
    15. 

  15. 

  16. #define RSTOUTn_MASK		(BRIDGE_VIRT_BASE + 0x0108)
    17. 

  17. #define RSTOUTn_MASK_PHYS	(BRIDGE_PHYS_BASE + 0x0108)
    18. 

  18. #define  SOFT_RESET_OUT_EN	0x00000004
    19. 

  19. 

  20. #define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)
    21. 

  21. #define  SOFT_RESET		0x00000001
    22. 

  22. 

  23. #define BRIDGE_CAUSE		(BRIDGE_VIRT_BASE + 0x0110)
    24. 

  24. #define  BRIDGE_INT_TIMER1_CLR	(~0x0004)
    25. 

  25. 

  26. #define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0200)
    27. 

  27. #define IRQ_CAUSE_LOW_OFF	0x0000
    28. 

  28. #define IRQ_MASK_LOW_OFF	0x0004
    29. 

  29. #define FIQ_MASK_LOW_OFF	0x0008
    30. 

  30. #define ENDPOINT_MASK_LOW_OFF	0x000c
    31. 

  31. #define IRQ_CAUSE_HIGH_OFF	0x0010
    32. 

  32. #define IRQ_MASK_HIGH_OFF	0x0014
    33. 

  33. #define FIQ_MASK_HIGH_OFF	0x0018
    34. 

  34. #define ENDPOINT_MASK_HIGH_OFF	0x001c
    35. 

  35. #define PCIE_INTERRUPT_MASK_OFF	0x0020
    36. 

  36. 

  37. #define IRQ_MASK_LOW		(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
    38. 

  38. #define FIQ_MASK_LOW		(IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
    39. 

  39. #define ENDPOINT_MASK_LOW	(IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
    40. 

  40. #define IRQ_MASK_HIGH		(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
    41. 

  41. #define FIQ_MASK_HIGH		(IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
    42. 

  42. #define ENDPOINT_MASK_HIGH	(IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
    43. 

  43. #define PCIE_INTERRUPT_MASK	(IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
    44. 

  44. 

  45. #define POWER_MANAGEMENT	(BRIDGE_VIRT_BASE + 0x011c)
    46. 

  46. 

  47. #define TIMER_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0300)
    48. 

  48. #define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
    49. 

  49. 

  50. #endif
    51.