pm.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2008 Cavium Networks
  4. */
  5. #include <linux/init.h>
  6. #include <linux/module.h>
  7. #include <linux/io.h>
  8. #include <linux/delay.h>
  9. #include <linux/atomic.h>
  10. #include "cns3xxx.h"
  11. #include "pm.h"
  12. #include "core.h"
  13. void cns3xxx_pwr_clk_en(unsigned int block)
  14. {
  15. u32 reg = __raw_readl(PM_CLK_GATE_REG);
  16. reg |= (block & PM_CLK_GATE_REG_MASK);
  17. __raw_writel(reg, PM_CLK_GATE_REG);
  18. }
  19. EXPORT_SYMBOL(cns3xxx_pwr_clk_en);
  20. void cns3xxx_pwr_clk_dis(unsigned int block)
  21. {
  22. u32 reg = __raw_readl(PM_CLK_GATE_REG);
  23. reg &= ~(block & PM_CLK_GATE_REG_MASK);
  24. __raw_writel(reg, PM_CLK_GATE_REG);
  25. }
  26. EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);
  27. void cns3xxx_pwr_power_up(unsigned int block)
  28. {
  29. u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
  30. reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
  31. __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
  32. /* Wait for 300us for the PLL output clock locked. */
  33. udelay(300);
  34. };
  35. EXPORT_SYMBOL(cns3xxx_pwr_power_up);
  36. void cns3xxx_pwr_power_down(unsigned int block)
  37. {
  38. u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
  39. /* write '1' to power down */
  40. reg |= (block & CNS3XXX_PWR_PLL_ALL);
  41. __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
  42. };
  43. EXPORT_SYMBOL(cns3xxx_pwr_power_down);
  44. static void cns3xxx_pwr_soft_rst_force(unsigned int block)
  45. {
  46. u32 reg = __raw_readl(PM_SOFT_RST_REG);
  47. /*
  48. * bit 0, 28, 29 => program low to reset,
  49. * the other else program low and then high
  50. */
  51. if (block & 0x30000001) {
  52. reg &= ~(block & PM_SOFT_RST_REG_MASK);
  53. } else {
  54. reg &= ~(block & PM_SOFT_RST_REG_MASK);
  55. __raw_writel(reg, PM_SOFT_RST_REG);
  56. reg |= (block & PM_SOFT_RST_REG_MASK);
  57. }
  58. __raw_writel(reg, PM_SOFT_RST_REG);
  59. }
  60. void cns3xxx_pwr_soft_rst(unsigned int block)
  61. {
  62. static unsigned int soft_reset;
  63. if (soft_reset & block) {
  64. /* SPI/I2C/GPIO use the same block, reset once. */
  65. return;
  66. } else {
  67. soft_reset |= block;
  68. }
  69. cns3xxx_pwr_soft_rst_force(block);
  70. }
  71. EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
  72. void cns3xxx_restart(enum reboot_mode mode, const char *cmd)
  73. {
  74. /*
  75. * To reset, we hit the on-board reset register
  76. * in the system FPGA.
  77. */
  78. cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
  79. }
  80. /*
  81. * cns3xxx_cpu_clock - return CPU/L2 clock
  82. * aclk: cpu clock/2
  83. * hclk: cpu clock/4
  84. * pclk: cpu clock/8
  85. */
  86. int cns3xxx_cpu_clock(void)
  87. {
  88. u32 reg = __raw_readl(PM_CLK_CTRL_REG);
  89. int cpu;
  90. int cpu_sel;
  91. int div_sel;
  92. cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
  93. div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
  94. cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
  95. return cpu;
  96. }
  97. EXPORT_SYMBOL(cns3xxx_cpu_clock);
  98. atomic_t usb_pwr_ref = ATOMIC_INIT(0);
  99. EXPORT_SYMBOL(usb_pwr_ref);