pm.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * arch/arm/mach-at91/pm.c
  4. * AT91 Power Management
  5. *
  6. * Copyright (C) 2005 David Brownell
  7. */
  8. #include <linux/genalloc.h>
  9. #include <linux/io.h>
  10. #include <linux/of_address.h>
  11. #include <linux/of.h>
  12. #include <linux/of_fdt.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/parser.h>
  15. #include <linux/suspend.h>
  16. #include <linux/clk.h>
  17. #include <linux/clk/at91_pmc.h>
  18. #include <linux/platform_data/atmel.h>
  19. #include <asm/cacheflush.h>
  20. #include <asm/fncpy.h>
  21. #include <asm/system_misc.h>
  22. #include <asm/suspend.h>
  23. #include "generic.h"
  24. #include "pm.h"
  25. #include "sam_secure.h"
  26. #define BACKUP_DDR_PHY_CALIBRATION (9)
  27. /**
  28. * struct at91_pm_bu - AT91 power management backup unit data structure
  29. * @suspended: true if suspended to backup mode
  30. * @reserved: reserved
  31. * @canary: canary data for memory checking after exit from backup mode
  32. * @resume: resume API
  33. * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words
  34. * of the memory
  35. */
  36. struct at91_pm_bu {
  37. int suspended;
  38. unsigned long reserved;
  39. phys_addr_t canary;
  40. phys_addr_t resume;
  41. unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];
  42. };
  43. /**
  44. * struct at91_pm_sfrbu_regs - registers mapping for SFRBU
  45. * @pswbu: power switch BU control registers
  46. */
  47. struct at91_pm_sfrbu_regs {
  48. struct {
  49. u32 key;
  50. u32 ctrl;
  51. u32 state;
  52. u32 softsw;
  53. } pswbu;
  54. };
  55. /**
  56. * enum at91_pm_eth_clk - Ethernet clock indexes
  57. * @AT91_PM_ETH_PCLK: pclk index
  58. * @AT91_PM_ETH_HCLK: hclk index
  59. * @AT91_PM_ETH_MAX_CLK: max index
  60. */
  61. enum at91_pm_eth_clk {
  62. AT91_PM_ETH_PCLK,
  63. AT91_PM_ETH_HCLK,
  64. AT91_PM_ETH_MAX_CLK,
  65. };
  66. /**
  67. * enum at91_pm_eth - Ethernet controller indexes
  68. * @AT91_PM_G_ETH: gigabit Ethernet controller index
  69. * @AT91_PM_E_ETH: megabit Ethernet controller index
  70. * @AT91_PM_MAX_ETH: max index
  71. */
  72. enum at91_pm_eth {
  73. AT91_PM_G_ETH,
  74. AT91_PM_E_ETH,
  75. AT91_PM_MAX_ETH,
  76. };
  77. /**
  78. * struct at91_pm_quirk_eth - AT91 PM Ethernet quirks
  79. * @dev: Ethernet device
  80. * @np: Ethernet device node
  81. * @clks: Ethernet clocks
  82. * @modes: power management mode that this quirk applies to
  83. * @dns_modes: do not suspend modes: stop suspending if Ethernet is configured
  84. * as wakeup source but buggy and no other wakeup source is
  85. * available
  86. */
  87. struct at91_pm_quirk_eth {
  88. struct device *dev;
  89. struct device_node *np;
  90. struct clk_bulk_data clks[AT91_PM_ETH_MAX_CLK];
  91. u32 modes;
  92. u32 dns_modes;
  93. };
  94. /**
  95. * struct at91_pm_quirks - AT91 PM quirks
  96. * @eth: Ethernet quirks
  97. */
  98. struct at91_pm_quirks {
  99. struct at91_pm_quirk_eth eth[AT91_PM_MAX_ETH];
  100. };
  101. /**
  102. * struct at91_soc_pm - AT91 SoC power management data structure
  103. * @config_shdwc_ws: wakeup sources configuration function for SHDWC
  104. * @config_pmc_ws: wakeup srouces configuration function for PMC
  105. * @ws_ids: wakup sources of_device_id array
  106. * @bu: backup unit mapped data (for backup mode)
  107. * @quirks: PM quirks
  108. * @data: PM data to be used on last phase of suspend
  109. * @sfrbu_regs: SFRBU registers mapping
  110. * @memcs: memory chip select
  111. */
  112. struct at91_soc_pm {
  113. int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
  114. int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
  115. const struct of_device_id *ws_ids;
  116. struct at91_pm_bu *bu;
  117. struct at91_pm_quirks quirks;
  118. struct at91_pm_data data;
  119. struct at91_pm_sfrbu_regs sfrbu_regs;
  120. void *memcs;
  121. };
  122. /**
  123. * enum at91_pm_iomaps - IOs that needs to be mapped for different PM modes
  124. * @AT91_PM_IOMAP_SHDWC: SHDWC controller
  125. * @AT91_PM_IOMAP_SFRBU: SFRBU controller
  126. * @AT91_PM_IOMAP_ETHC: Ethernet controller
  127. */
  128. enum at91_pm_iomaps {
  129. AT91_PM_IOMAP_SHDWC,
  130. AT91_PM_IOMAP_SFRBU,
  131. AT91_PM_IOMAP_ETHC,
  132. };
  133. #define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name)
  134. static struct at91_soc_pm soc_pm = {
  135. .data = {
  136. .standby_mode = AT91_PM_STANDBY,
  137. .suspend_mode = AT91_PM_ULP0,
  138. },
  139. };
  140. static const match_table_t pm_modes __initconst = {
  141. { AT91_PM_STANDBY, "standby" },
  142. { AT91_PM_ULP0, "ulp0" },
  143. { AT91_PM_ULP0_FAST, "ulp0-fast" },
  144. { AT91_PM_ULP1, "ulp1" },
  145. { AT91_PM_BACKUP, "backup" },
  146. { -1, NULL },
  147. };
  148. #define at91_ramc_read(id, field) \
  149. __raw_readl(soc_pm.data.ramc[id] + field)
  150. #define at91_ramc_write(id, field, value) \
  151. __raw_writel(value, soc_pm.data.ramc[id] + field)
  152. static int at91_pm_valid_state(suspend_state_t state)
  153. {
  154. switch (state) {
  155. case PM_SUSPEND_ON:
  156. case PM_SUSPEND_STANDBY:
  157. case PM_SUSPEND_MEM:
  158. return 1;
  159. default:
  160. return 0;
  161. }
  162. }
  163. static int canary = 0xA5A5A5A5;
  164. struct wakeup_source_info {
  165. unsigned int pmc_fsmr_bit;
  166. unsigned int shdwc_mr_bit;
  167. bool set_polarity;
  168. };
  169. static const struct wakeup_source_info ws_info[] = {
  170. { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
  171. { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
  172. { .pmc_fsmr_bit = AT91_PMC_USBAL },
  173. { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
  174. { .pmc_fsmr_bit = AT91_PMC_RTTAL },
  175. { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
  176. };
  177. static const struct of_device_id sama5d2_ws_ids[] = {
  178. { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
  179. { .compatible = "atmel,sama5d2-rtc", .data = &ws_info[1] },
  180. { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
  181. { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
  182. { .compatible = "usb-ohci", .data = &ws_info[2] },
  183. { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
  184. { .compatible = "usb-ehci", .data = &ws_info[2] },
  185. { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
  186. { /* sentinel */ }
  187. };
  188. static const struct of_device_id sam9x60_ws_ids[] = {
  189. { .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] },
  190. { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
  191. { .compatible = "usb-ohci", .data = &ws_info[2] },
  192. { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
  193. { .compatible = "usb-ehci", .data = &ws_info[2] },
  194. { .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] },
  195. { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
  196. { /* sentinel */ }
  197. };
  198. static const struct of_device_id sama7g5_ws_ids[] = {
  199. { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] },
  200. { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] },
  201. { .compatible = "usb-ohci", .data = &ws_info[2] },
  202. { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
  203. { .compatible = "usb-ehci", .data = &ws_info[2] },
  204. { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] },
  205. { .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] },
  206. { /* sentinel */ }
  207. };
  208. static int at91_pm_config_ws(unsigned int pm_mode, bool set)
  209. {
  210. const struct wakeup_source_info *wsi;
  211. const struct of_device_id *match;
  212. struct platform_device *pdev;
  213. struct device_node *np;
  214. unsigned int mode = 0, polarity = 0, val = 0;
  215. if (pm_mode != AT91_PM_ULP1)
  216. return 0;
  217. if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
  218. return -EPERM;
  219. if (!set) {
  220. writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
  221. return 0;
  222. }
  223. if (soc_pm.config_shdwc_ws)
  224. soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
  225. /* SHDWC.MR */
  226. val = readl(soc_pm.data.shdwc + 0x04);
  227. /* Loop through defined wakeup sources. */
  228. for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
  229. pdev = of_find_device_by_node(np);
  230. if (!pdev)
  231. continue;
  232. if (device_may_wakeup(&pdev->dev)) {
  233. wsi = match->data;
  234. /* Check if enabled on SHDWC. */
  235. if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
  236. goto put_device;
  237. mode |= wsi->pmc_fsmr_bit;
  238. if (wsi->set_polarity)
  239. polarity |= wsi->pmc_fsmr_bit;
  240. }
  241. put_device:
  242. put_device(&pdev->dev);
  243. }
  244. if (mode) {
  245. if (soc_pm.config_pmc_ws)
  246. soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
  247. } else {
  248. pr_err("AT91: PM: no ULP1 wakeup sources found!");
  249. }
  250. return mode ? 0 : -EPERM;
  251. }
  252. static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
  253. u32 *polarity)
  254. {
  255. u32 val;
  256. /* SHDWC.WUIR */
  257. val = readl(shdwc + 0x0c);
  258. *mode |= (val & 0x3ff);
  259. *polarity |= ((val >> 16) & 0x3ff);
  260. return 0;
  261. }
  262. static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
  263. {
  264. writel(mode, pmc + AT91_PMC_FSMR);
  265. writel(polarity, pmc + AT91_PMC_FSPR);
  266. return 0;
  267. }
  268. static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
  269. {
  270. writel(mode, pmc + AT91_PMC_FSMR);
  271. return 0;
  272. }
  273. static bool at91_pm_eth_quirk_is_valid(struct at91_pm_quirk_eth *eth)
  274. {
  275. struct platform_device *pdev;
  276. /* Interface NA in DT. */
  277. if (!eth->np)
  278. return false;
  279. /* No quirks for this interface and current suspend mode. */
  280. if (!(eth->modes & BIT(soc_pm.data.mode)))
  281. return false;
  282. if (!eth->dev) {
  283. /* Driver not probed. */
  284. pdev = of_find_device_by_node(eth->np);
  285. if (!pdev)
  286. return false;
  287. /* put_device(eth->dev) is called at the end of suspend. */
  288. eth->dev = &pdev->dev;
  289. }
  290. /* No quirks if device isn't a wakeup source. */
  291. if (!device_may_wakeup(eth->dev))
  292. return false;
  293. return true;
  294. }
  295. static int at91_pm_config_quirks(bool suspend)
  296. {
  297. struct at91_pm_quirk_eth *eth;
  298. int i, j, ret, tmp;
  299. /*
  300. * Ethernet IPs who's device_node pointers are stored into
  301. * soc_pm.quirks.eth[].np cannot handle WoL packets while in ULP0, ULP1
  302. * or both due to a hardware bug. If they receive WoL packets while in
  303. * ULP0 or ULP1 IPs could stop working or the whole system could stop
  304. * working. We cannot handle this scenario in the ethernet driver itself
  305. * as the driver is common to multiple vendors and also we only know
  306. * here, in this file, if we suspend to ULP0 or ULP1 mode. Thus handle
  307. * these scenarios here, as quirks.
  308. */
  309. for (i = 0; i < AT91_PM_MAX_ETH; i++) {
  310. eth = &soc_pm.quirks.eth[i];
  311. if (!at91_pm_eth_quirk_is_valid(eth))
  312. continue;
  313. /*
  314. * For modes in dns_modes mask the system blocks if quirk is not
  315. * applied but if applied the interface doesn't act at WoL
  316. * events. Thus take care to avoid suspending if this interface
  317. * is the only configured wakeup source.
  318. */
  319. if (suspend && eth->dns_modes & BIT(soc_pm.data.mode)) {
  320. int ws_count = 0;
  321. #ifdef CONFIG_PM_SLEEP
  322. struct wakeup_source *ws;
  323. for_each_wakeup_source(ws) {
  324. if (ws->dev == eth->dev)
  325. continue;
  326. ws_count++;
  327. break;
  328. }
  329. #endif
  330. /*
  331. * Checking !ws is good for all platforms with issues
  332. * even when both G_ETH and E_ETH are available as dns_modes
  333. * is populated only on G_ETH interface.
  334. */
  335. if (!ws_count) {
  336. pr_err("AT91: PM: Ethernet cannot resume from WoL!");
  337. ret = -EPERM;
  338. put_device(eth->dev);
  339. eth->dev = NULL;
  340. /* No need to revert clock settings for this eth. */
  341. i--;
  342. goto clk_unconfigure;
  343. }
  344. }
  345. if (suspend) {
  346. clk_bulk_disable_unprepare(AT91_PM_ETH_MAX_CLK, eth->clks);
  347. } else {
  348. ret = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK,
  349. eth->clks);
  350. if (ret)
  351. goto clk_unconfigure;
  352. /*
  353. * Release the reference to eth->dev taken in
  354. * at91_pm_eth_quirk_is_valid().
  355. */
  356. put_device(eth->dev);
  357. eth->dev = NULL;
  358. }
  359. }
  360. return 0;
  361. clk_unconfigure:
  362. /*
  363. * In case of resume we reach this point if clk_prepare_enable() failed.
  364. * we don't want to revert the previous clk_prepare_enable() for the
  365. * other IP.
  366. */
  367. for (j = i; j >= 0; j--) {
  368. eth = &soc_pm.quirks.eth[j];
  369. if (suspend) {
  370. if (!at91_pm_eth_quirk_is_valid(eth))
  371. continue;
  372. tmp = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK, eth->clks);
  373. if (tmp) {
  374. pr_err("AT91: PM: failed to enable %s clocks\n",
  375. j == AT91_PM_G_ETH ? "geth" : "eth");
  376. }
  377. }
  378. /*
  379. * Release the reference to eth->dev taken in
  380. * at91_pm_eth_quirk_is_valid().
  381. */
  382. put_device(eth->dev);
  383. eth->dev = NULL;
  384. }
  385. return ret;
  386. }
  387. /*
  388. * Called after processes are frozen, but before we shutdown devices.
  389. */
  390. static int at91_pm_begin(suspend_state_t state)
  391. {
  392. int ret;
  393. switch (state) {
  394. case PM_SUSPEND_MEM:
  395. soc_pm.data.mode = soc_pm.data.suspend_mode;
  396. break;
  397. case PM_SUSPEND_STANDBY:
  398. soc_pm.data.mode = soc_pm.data.standby_mode;
  399. break;
  400. default:
  401. soc_pm.data.mode = -1;
  402. }
  403. ret = at91_pm_config_ws(soc_pm.data.mode, true);
  404. if (ret)
  405. return ret;
  406. if (soc_pm.data.mode == AT91_PM_BACKUP)
  407. soc_pm.bu->suspended = 1;
  408. else if (soc_pm.bu)
  409. soc_pm.bu->suspended = 0;
  410. return 0;
  411. }
  412. /*
  413. * Verify that all the clocks are correct before entering
  414. * slow-clock mode.
  415. */
  416. static int at91_pm_verify_clocks(void)
  417. {
  418. unsigned long scsr;
  419. int i;
  420. scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
  421. /* USB must not be using PLLB */
  422. if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
  423. pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
  424. return 0;
  425. }
  426. /* PCK0..PCK3 must be disabled, or configured to use clk32k */
  427. for (i = 0; i < 4; i++) {
  428. u32 css;
  429. if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
  430. continue;
  431. css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
  432. if (css != AT91_PMC_CSS_SLOW) {
  433. pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
  434. return 0;
  435. }
  436. }
  437. return 1;
  438. }
  439. /*
  440. * Call this from platform driver suspend() to see how deeply to suspend.
  441. * For example, some controllers (like OHCI) need one of the PLL clocks
  442. * in order to act as a wakeup source, and those are not available when
  443. * going into slow clock mode.
  444. *
  445. * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
  446. * the very same problem (but not using at91 main_clk), and it'd be better
  447. * to add one generic API rather than lots of platform-specific ones.
  448. */
  449. int at91_suspend_entering_slow_clock(void)
  450. {
  451. return (soc_pm.data.mode >= AT91_PM_ULP0);
  452. }
  453. EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
  454. static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
  455. extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
  456. extern u32 at91_pm_suspend_in_sram_sz;
  457. static int at91_suspend_finish(unsigned long val)
  458. {
  459. unsigned char modified_gray_code[] = {
  460. 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d,
  461. 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b,
  462. 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13,
  463. 0x10, 0x11,
  464. };
  465. unsigned int tmp, index;
  466. int i;
  467. if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
  468. /*
  469. * Bootloader will perform DDR recalibration and will try to
  470. * restore the ZQ0SR0 with the value saved here. But the
  471. * calibration is buggy and restoring some values from ZQ0SR0
  472. * is forbidden and risky thus we need to provide processed
  473. * values for these (modified gray code values).
  474. */
  475. tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
  476. /* Store pull-down output impedance select. */
  477. index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f;
  478. soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index];
  479. /* Store pull-up output impedance select. */
  480. index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f;
  481. soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
  482. /* Store pull-down on-die termination impedance select. */
  483. index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f;
  484. soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
  485. /* Store pull-up on-die termination impedance select. */
  486. index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f;
  487. soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
  488. /*
  489. * The 1st 8 words of memory might get corrupted in the process
  490. * of DDR PHY recalibration; it is saved here in securam and it
  491. * will be restored later, after recalibration, by bootloader
  492. */
  493. for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++)
  494. soc_pm.bu->ddr_phy_calibration[i] =
  495. *((unsigned int *)soc_pm.memcs + (i - 1));
  496. }
  497. flush_cache_all();
  498. outer_disable();
  499. at91_suspend_sram_fn(&soc_pm.data);
  500. return 0;
  501. }
  502. static void at91_pm_switch_ba_to_vbat(void)
  503. {
  504. unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu);
  505. unsigned int val;
  506. /* Just for safety. */
  507. if (!soc_pm.data.sfrbu)
  508. return;
  509. val = readl(soc_pm.data.sfrbu + offset);
  510. /* Already on VBAT. */
  511. if (!(val & soc_pm.sfrbu_regs.pswbu.state))
  512. return;
  513. val &= ~soc_pm.sfrbu_regs.pswbu.softsw;
  514. val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl;
  515. writel(val, soc_pm.data.sfrbu + offset);
  516. /* Wait for update. */
  517. val = readl(soc_pm.data.sfrbu + offset);
  518. while (val & soc_pm.sfrbu_regs.pswbu.state)
  519. val = readl(soc_pm.data.sfrbu + offset);
  520. }
  521. static void at91_pm_suspend(suspend_state_t state)
  522. {
  523. if (soc_pm.data.mode == AT91_PM_BACKUP) {
  524. at91_pm_switch_ba_to_vbat();
  525. cpu_suspend(0, at91_suspend_finish);
  526. /* The SRAM is lost between suspend cycles */
  527. at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
  528. &at91_pm_suspend_in_sram,
  529. at91_pm_suspend_in_sram_sz);
  530. } else {
  531. at91_suspend_finish(0);
  532. }
  533. outer_resume();
  534. }
  535. /*
  536. * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
  537. * event sources; and reduces DRAM power. But otherwise it's identical to
  538. * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
  539. *
  540. * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
  541. * suspend more deeply, the master clock switches to the clk32k and turns off
  542. * the main oscillator
  543. *
  544. * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
  545. */
  546. static int at91_pm_enter(suspend_state_t state)
  547. {
  548. int ret;
  549. ret = at91_pm_config_quirks(true);
  550. if (ret)
  551. return ret;
  552. switch (state) {
  553. case PM_SUSPEND_MEM:
  554. case PM_SUSPEND_STANDBY:
  555. /*
  556. * Ensure that clocks are in a valid state.
  557. */
  558. if (soc_pm.data.mode >= AT91_PM_ULP0 &&
  559. !at91_pm_verify_clocks())
  560. goto error;
  561. at91_pm_suspend(state);
  562. break;
  563. case PM_SUSPEND_ON:
  564. cpu_do_idle();
  565. break;
  566. default:
  567. pr_debug("AT91: PM - bogus suspend state %d\n", state);
  568. goto error;
  569. }
  570. error:
  571. at91_pm_config_quirks(false);
  572. return 0;
  573. }
  574. /*
  575. * Called right prior to thawing processes.
  576. */
  577. static void at91_pm_end(void)
  578. {
  579. at91_pm_config_ws(soc_pm.data.mode, false);
  580. }
  581. static const struct platform_suspend_ops at91_pm_ops = {
  582. .valid = at91_pm_valid_state,
  583. .begin = at91_pm_begin,
  584. .enter = at91_pm_enter,
  585. .end = at91_pm_end,
  586. };
  587. static struct platform_device at91_cpuidle_device = {
  588. .name = "cpuidle-at91",
  589. };
  590. /*
  591. * The AT91RM9200 goes into self-refresh mode with this command, and will
  592. * terminate self-refresh automatically on the next SDRAM access.
  593. *
  594. * Self-refresh mode is exited as soon as a memory access is made, but we don't
  595. * know for sure when that happens. However, we need to restore the low-power
  596. * mode if it was enabled before going idle. Restoring low-power mode while
  597. * still in self-refresh is "not recommended", but seems to work.
  598. */
  599. static void at91rm9200_standby(void)
  600. {
  601. asm volatile(
  602. "b 1f\n\t"
  603. ".align 5\n\t"
  604. "1: mcr p15, 0, %0, c7, c10, 4\n\t"
  605. " str %2, [%1, %3]\n\t"
  606. " mcr p15, 0, %0, c7, c0, 4\n\t"
  607. :
  608. : "r" (0), "r" (soc_pm.data.ramc[0]),
  609. "r" (1), "r" (AT91_MC_SDRAMC_SRR));
  610. }
  611. /* We manage both DDRAM/SDRAM controllers, we need more than one value to
  612. * remember.
  613. */
  614. static void at91_ddr_standby(void)
  615. {
  616. /* Those two values allow us to delay self-refresh activation
  617. * to the maximum. */
  618. u32 lpr0, lpr1 = 0;
  619. u32 mdr, saved_mdr0, saved_mdr1 = 0;
  620. u32 saved_lpr0, saved_lpr1 = 0;
  621. /* LPDDR1 --> force DDR2 mode during self-refresh */
  622. saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
  623. if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
  624. mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
  625. mdr |= AT91_DDRSDRC_MD_DDR2;
  626. at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
  627. }
  628. if (soc_pm.data.ramc[1]) {
  629. saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
  630. lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
  631. lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
  632. saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
  633. if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
  634. mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
  635. mdr |= AT91_DDRSDRC_MD_DDR2;
  636. at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
  637. }
  638. }
  639. saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
  640. lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
  641. lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
  642. /* self-refresh mode now */
  643. at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
  644. if (soc_pm.data.ramc[1])
  645. at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
  646. cpu_do_idle();
  647. at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
  648. at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
  649. if (soc_pm.data.ramc[1]) {
  650. at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
  651. at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
  652. }
  653. }
  654. static void sama5d3_ddr_standby(void)
  655. {
  656. u32 lpr0;
  657. u32 saved_lpr0;
  658. saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
  659. lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
  660. lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
  661. at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
  662. cpu_do_idle();
  663. at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
  664. }
  665. /* We manage both DDRAM/SDRAM controllers, we need more than one value to
  666. * remember.
  667. */
  668. static void at91sam9_sdram_standby(void)
  669. {
  670. u32 lpr0, lpr1 = 0;
  671. u32 saved_lpr0, saved_lpr1 = 0;
  672. if (soc_pm.data.ramc[1]) {
  673. saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
  674. lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
  675. lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
  676. }
  677. saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
  678. lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
  679. lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
  680. /* self-refresh mode now */
  681. at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
  682. if (soc_pm.data.ramc[1])
  683. at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
  684. cpu_do_idle();
  685. at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
  686. if (soc_pm.data.ramc[1])
  687. at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
  688. }
  689. static void sama7g5_standby(void)
  690. {
  691. int pwrtmg, ratio;
  692. pwrtmg = readl(soc_pm.data.ramc[0] + UDDRC_PWRCTL);
  693. ratio = readl(soc_pm.data.pmc + AT91_PMC_RATIO);
  694. /*
  695. * Place RAM into self-refresh after a maximum idle clocks. The maximum
  696. * idle clocks is configured by bootloader in
  697. * UDDRC_PWRMGT.SELFREF_TO_X32.
  698. */
  699. writel(pwrtmg | UDDRC_PWRCTL_SELFREF_EN,
  700. soc_pm.data.ramc[0] + UDDRC_PWRCTL);
  701. /* Divide CPU clock by 16. */
  702. writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO);
  703. cpu_do_idle();
  704. /* Restore previous configuration. */
  705. writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO);
  706. writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL);
  707. }
  708. struct ramc_info {
  709. void (*idle)(void);
  710. unsigned int memctrl;
  711. };
  712. static const struct ramc_info ramc_infos[] __initconst = {
  713. { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
  714. { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
  715. { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
  716. { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
  717. { .idle = sama7g5_standby, },
  718. };
  719. static const struct of_device_id ramc_ids[] __initconst = {
  720. { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
  721. { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
  722. { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
  723. { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
  724. { .compatible = "microchip,sama7g5-uddrc", .data = &ramc_infos[4], },
  725. { /*sentinel*/ }
  726. };
  727. static const struct of_device_id ramc_phy_ids[] __initconst = {
  728. { .compatible = "microchip,sama7g5-ddr3phy", },
  729. { /* Sentinel. */ },
  730. };
  731. static __init int at91_dt_ramc(bool phy_mandatory)
  732. {
  733. struct device_node *np;
  734. const struct of_device_id *of_id;
  735. int idx = 0;
  736. void *standby = NULL;
  737. const struct ramc_info *ramc;
  738. int ret;
  739. for_each_matching_node_and_match(np, ramc_ids, &of_id) {
  740. soc_pm.data.ramc[idx] = of_iomap(np, 0);
  741. if (!soc_pm.data.ramc[idx]) {
  742. pr_err("unable to map ramc[%d] cpu registers\n", idx);
  743. ret = -ENOMEM;
  744. of_node_put(np);
  745. goto unmap_ramc;
  746. }
  747. ramc = of_id->data;
  748. if (ramc) {
  749. if (!standby)
  750. standby = ramc->idle;
  751. soc_pm.data.memctrl = ramc->memctrl;
  752. }
  753. idx++;
  754. }
  755. if (!idx) {
  756. pr_err("unable to find compatible ram controller node in dtb\n");
  757. ret = -ENODEV;
  758. goto unmap_ramc;
  759. }
  760. /* Lookup for DDR PHY node, if any. */
  761. for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) {
  762. soc_pm.data.ramc_phy = of_iomap(np, 0);
  763. if (!soc_pm.data.ramc_phy) {
  764. pr_err("unable to map ramc phy cpu registers\n");
  765. ret = -ENOMEM;
  766. of_node_put(np);
  767. goto unmap_ramc;
  768. }
  769. }
  770. if (phy_mandatory && !soc_pm.data.ramc_phy) {
  771. pr_err("DDR PHY is mandatory!\n");
  772. ret = -ENODEV;
  773. goto unmap_ramc;
  774. }
  775. if (!standby) {
  776. pr_warn("ramc no standby function available\n");
  777. return 0;
  778. }
  779. at91_cpuidle_device.dev.platform_data = standby;
  780. return 0;
  781. unmap_ramc:
  782. while (idx)
  783. iounmap(soc_pm.data.ramc[--idx]);
  784. return ret;
  785. }
  786. static void at91rm9200_idle(void)
  787. {
  788. /*
  789. * Disable the processor clock. The processor will be automatically
  790. * re-enabled by an interrupt or by a reset.
  791. */
  792. writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
  793. }
  794. static void at91sam9_idle(void)
  795. {
  796. writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
  797. cpu_do_idle();
  798. }
  799. static void __init at91_pm_sram_init(void)
  800. {
  801. struct gen_pool *sram_pool;
  802. phys_addr_t sram_pbase;
  803. unsigned long sram_base;
  804. struct device_node *node;
  805. struct platform_device *pdev = NULL;
  806. for_each_compatible_node(node, NULL, "mmio-sram") {
  807. pdev = of_find_device_by_node(node);
  808. if (pdev) {
  809. of_node_put(node);
  810. break;
  811. }
  812. }
  813. if (!pdev) {
  814. pr_warn("%s: failed to find sram device!\n", __func__);
  815. return;
  816. }
  817. sram_pool = gen_pool_get(&pdev->dev, NULL);
  818. if (!sram_pool) {
  819. pr_warn("%s: sram pool unavailable!\n", __func__);
  820. goto out_put_device;
  821. }
  822. sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
  823. if (!sram_base) {
  824. pr_warn("%s: unable to alloc sram!\n", __func__);
  825. goto out_put_device;
  826. }
  827. sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
  828. at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
  829. at91_pm_suspend_in_sram_sz, false);
  830. if (!at91_suspend_sram_fn) {
  831. pr_warn("SRAM: Could not map\n");
  832. goto out_put_device;
  833. }
  834. /* Copy the pm suspend handler to SRAM */
  835. at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
  836. &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
  837. return;
  838. out_put_device:
  839. put_device(&pdev->dev);
  840. return;
  841. }
  842. static bool __init at91_is_pm_mode_active(int pm_mode)
  843. {
  844. return (soc_pm.data.standby_mode == pm_mode ||
  845. soc_pm.data.suspend_mode == pm_mode);
  846. }
  847. static int __init at91_pm_backup_scan_memcs(unsigned long node,
  848. const char *uname, int depth,
  849. void *data)
  850. {
  851. const char *type;
  852. const __be32 *reg;
  853. int *located = data;
  854. int size;
  855. /* Memory node already located. */
  856. if (*located)
  857. return 0;
  858. type = of_get_flat_dt_prop(node, "device_type", NULL);
  859. /* We are scanning "memory" nodes only. */
  860. if (!type || strcmp(type, "memory"))
  861. return 0;
  862. reg = of_get_flat_dt_prop(node, "reg", &size);
  863. if (reg) {
  864. soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg));
  865. *located = 1;
  866. }
  867. return 0;
  868. }
  869. static int __init at91_pm_backup_init(void)
  870. {
  871. struct gen_pool *sram_pool;
  872. struct device_node *np;
  873. struct platform_device *pdev;
  874. int ret = -ENODEV, located = 0;
  875. if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&
  876. !IS_ENABLED(CONFIG_SOC_SAMA7G5))
  877. return -EPERM;
  878. if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
  879. return 0;
  880. np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
  881. if (!np)
  882. return ret;
  883. pdev = of_find_device_by_node(np);
  884. of_node_put(np);
  885. if (!pdev) {
  886. pr_warn("%s: failed to find securam device!\n", __func__);
  887. return ret;
  888. }
  889. sram_pool = gen_pool_get(&pdev->dev, NULL);
  890. if (!sram_pool) {
  891. pr_warn("%s: securam pool unavailable!\n", __func__);
  892. goto securam_fail;
  893. }
  894. soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
  895. if (!soc_pm.bu) {
  896. pr_warn("%s: unable to alloc securam!\n", __func__);
  897. ret = -ENOMEM;
  898. goto securam_fail;
  899. }
  900. soc_pm.bu->suspended = 0;
  901. soc_pm.bu->canary = __pa_symbol(&canary);
  902. soc_pm.bu->resume = __pa_symbol(cpu_resume);
  903. if (soc_pm.data.ramc_phy) {
  904. of_scan_flat_dt(at91_pm_backup_scan_memcs, &located);
  905. if (!located)
  906. goto securam_fail;
  907. }
  908. return 0;
  909. securam_fail:
  910. put_device(&pdev->dev);
  911. return ret;
  912. }
  913. static void __init at91_pm_secure_init(void)
  914. {
  915. int suspend_mode;
  916. struct arm_smccc_res res;
  917. suspend_mode = soc_pm.data.suspend_mode;
  918. res = sam_smccc_call(SAMA5_SMC_SIP_SET_SUSPEND_MODE,
  919. suspend_mode, 0);
  920. if (res.a0 == 0) {
  921. pr_info("AT91: Secure PM: suspend mode set to %s\n",
  922. pm_modes[suspend_mode].pattern);
  923. return;
  924. }
  925. pr_warn("AT91: Secure PM: %s mode not supported !\n",
  926. pm_modes[suspend_mode].pattern);
  927. res = sam_smccc_call(SAMA5_SMC_SIP_GET_SUSPEND_MODE, 0, 0);
  928. if (res.a0 == 0) {
  929. pr_warn("AT91: Secure PM: failed to get default mode\n");
  930. return;
  931. }
  932. pr_info("AT91: Secure PM: using default suspend mode %s\n",
  933. pm_modes[suspend_mode].pattern);
  934. soc_pm.data.suspend_mode = res.a1;
  935. }
  936. static const struct of_device_id atmel_shdwc_ids[] = {
  937. { .compatible = "atmel,sama5d2-shdwc" },
  938. { .compatible = "microchip,sam9x60-shdwc" },
  939. { .compatible = "microchip,sama7g5-shdwc" },
  940. { /* sentinel. */ }
  941. };
  942. static const struct of_device_id gmac_ids[] __initconst = {
  943. { .compatible = "atmel,sama5d3-gem" },
  944. { .compatible = "atmel,sama5d2-gem" },
  945. { .compatible = "atmel,sama5d29-gem" },
  946. { .compatible = "microchip,sama7g5-gem" },
  947. { },
  948. };
  949. static const struct of_device_id emac_ids[] __initconst = {
  950. { .compatible = "atmel,sama5d3-macb" },
  951. { .compatible = "microchip,sama7g5-emac" },
  952. { },
  953. };
  954. /*
  955. * Replaces _mode_to_replace with a supported mode that doesn't depend
  956. * on controller pointed by _map_bitmask
  957. * @_maps: u32 array containing AT91_PM_IOMAP() flags and indexed by AT91
  958. * PM mode
  959. * @_map_bitmask: AT91_PM_IOMAP() bitmask; if _mode_to_replace depends on
  960. * controller represented by _map_bitmask, _mode_to_replace needs to be
  961. * updated
  962. * @_mode_to_replace: standby_mode or suspend_mode that need to be
  963. * updated
  964. * @_mode_to_check: standby_mode or suspend_mode; this is needed here
  965. * to avoid having standby_mode and suspend_mode set with the same AT91
  966. * PM mode
  967. */
  968. #define AT91_PM_REPLACE_MODE(_maps, _map_bitmask, _mode_to_replace, \
  969. _mode_to_check) \
  970. do { \
  971. if (((_maps)[(_mode_to_replace)]) & (_map_bitmask)) { \
  972. int _mode_to_use, _mode_complementary; \
  973. /* Use ULP0 if it doesn't need _map_bitmask. */ \
  974. if (!((_maps)[AT91_PM_ULP0] & (_map_bitmask))) {\
  975. _mode_to_use = AT91_PM_ULP0; \
  976. _mode_complementary = AT91_PM_STANDBY; \
  977. } else { \
  978. _mode_to_use = AT91_PM_STANDBY; \
  979. _mode_complementary = AT91_PM_STANDBY; \
  980. } \
  981. \
  982. if ((_mode_to_check) != _mode_to_use) \
  983. (_mode_to_replace) = _mode_to_use; \
  984. else \
  985. (_mode_to_replace) = _mode_complementary;\
  986. } \
  987. } while (0)
  988. /*
  989. * Replaces standby and suspend modes with default supported modes:
  990. * ULP0 and STANDBY.
  991. * @_maps: u32 array indexed by AT91 PM mode containing AT91_PM_IOMAP()
  992. * flags
  993. * @_map: controller specific name; standby and suspend mode need to be
  994. * replaced in order to not depend on this controller
  995. */
  996. #define AT91_PM_REPLACE_MODES(_maps, _map) \
  997. do { \
  998. AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\
  999. (soc_pm.data.standby_mode), \
  1000. (soc_pm.data.suspend_mode)); \
  1001. AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\
  1002. (soc_pm.data.suspend_mode), \
  1003. (soc_pm.data.standby_mode)); \
  1004. } while (0)
  1005. static int __init at91_pm_get_eth_clks(struct device_node *np,
  1006. struct clk_bulk_data *clks)
  1007. {
  1008. clks[AT91_PM_ETH_PCLK].clk = of_clk_get_by_name(np, "pclk");
  1009. if (IS_ERR(clks[AT91_PM_ETH_PCLK].clk))
  1010. return PTR_ERR(clks[AT91_PM_ETH_PCLK].clk);
  1011. clks[AT91_PM_ETH_HCLK].clk = of_clk_get_by_name(np, "hclk");
  1012. if (IS_ERR(clks[AT91_PM_ETH_HCLK].clk))
  1013. return PTR_ERR(clks[AT91_PM_ETH_HCLK].clk);
  1014. return 0;
  1015. }
  1016. static int __init at91_pm_eth_clks_empty(struct clk_bulk_data *clks)
  1017. {
  1018. return IS_ERR(clks[AT91_PM_ETH_PCLK].clk) ||
  1019. IS_ERR(clks[AT91_PM_ETH_HCLK].clk);
  1020. }
  1021. static void __init at91_pm_modes_init(const u32 *maps, int len)
  1022. {
  1023. struct at91_pm_quirk_eth *gmac = &soc_pm.quirks.eth[AT91_PM_G_ETH];
  1024. struct at91_pm_quirk_eth *emac = &soc_pm.quirks.eth[AT91_PM_E_ETH];
  1025. struct device_node *np;
  1026. int ret;
  1027. ret = at91_pm_backup_init();
  1028. if (ret) {
  1029. if (soc_pm.data.standby_mode == AT91_PM_BACKUP)
  1030. soc_pm.data.standby_mode = AT91_PM_ULP0;
  1031. if (soc_pm.data.suspend_mode == AT91_PM_BACKUP)
  1032. soc_pm.data.suspend_mode = AT91_PM_ULP0;
  1033. }
  1034. if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
  1035. maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) {
  1036. np = of_find_matching_node(NULL, atmel_shdwc_ids);
  1037. if (!np) {
  1038. pr_warn("%s: failed to find shdwc!\n", __func__);
  1039. AT91_PM_REPLACE_MODES(maps, SHDWC);
  1040. } else {
  1041. soc_pm.data.shdwc = of_iomap(np, 0);
  1042. of_node_put(np);
  1043. }
  1044. }
  1045. if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
  1046. maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) {
  1047. np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
  1048. if (!np) {
  1049. pr_warn("%s: failed to find sfrbu!\n", __func__);
  1050. AT91_PM_REPLACE_MODES(maps, SFRBU);
  1051. } else {
  1052. soc_pm.data.sfrbu = of_iomap(np, 0);
  1053. of_node_put(np);
  1054. }
  1055. }
  1056. if ((at91_is_pm_mode_active(AT91_PM_ULP1) ||
  1057. at91_is_pm_mode_active(AT91_PM_ULP0) ||
  1058. at91_is_pm_mode_active(AT91_PM_ULP0_FAST)) &&
  1059. (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(ETHC) ||
  1060. maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(ETHC))) {
  1061. np = of_find_matching_node(NULL, gmac_ids);
  1062. if (!np) {
  1063. np = of_find_matching_node(NULL, emac_ids);
  1064. if (np)
  1065. goto get_emac_clks;
  1066. AT91_PM_REPLACE_MODES(maps, ETHC);
  1067. goto unmap_unused_nodes;
  1068. } else {
  1069. gmac->np = np;
  1070. at91_pm_get_eth_clks(np, gmac->clks);
  1071. }
  1072. np = of_find_matching_node(NULL, emac_ids);
  1073. if (!np) {
  1074. if (at91_pm_eth_clks_empty(gmac->clks))
  1075. AT91_PM_REPLACE_MODES(maps, ETHC);
  1076. } else {
  1077. get_emac_clks:
  1078. emac->np = np;
  1079. ret = at91_pm_get_eth_clks(np, emac->clks);
  1080. if (ret && at91_pm_eth_clks_empty(gmac->clks)) {
  1081. of_node_put(gmac->np);
  1082. of_node_put(emac->np);
  1083. gmac->np = NULL;
  1084. emac->np = NULL;
  1085. }
  1086. }
  1087. }
  1088. unmap_unused_nodes:
  1089. /* Unmap all unnecessary. */
  1090. if (soc_pm.data.shdwc &&
  1091. !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
  1092. maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) {
  1093. iounmap(soc_pm.data.shdwc);
  1094. soc_pm.data.shdwc = NULL;
  1095. }
  1096. if (soc_pm.data.sfrbu &&
  1097. !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
  1098. maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) {
  1099. iounmap(soc_pm.data.sfrbu);
  1100. soc_pm.data.sfrbu = NULL;
  1101. }
  1102. return;
  1103. }
  1104. struct pmc_info {
  1105. unsigned long uhp_udp_mask;
  1106. unsigned long mckr;
  1107. unsigned long version;
  1108. };
  1109. static const struct pmc_info pmc_infos[] __initconst = {
  1110. {
  1111. .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
  1112. .mckr = 0x30,
  1113. .version = AT91_PMC_V1,
  1114. },
  1115. {
  1116. .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
  1117. .mckr = 0x30,
  1118. .version = AT91_PMC_V1,
  1119. },
  1120. {
  1121. .uhp_udp_mask = AT91SAM926x_PMC_UHP,
  1122. .mckr = 0x30,
  1123. .version = AT91_PMC_V1,
  1124. },
  1125. { .uhp_udp_mask = 0,
  1126. .mckr = 0x30,
  1127. .version = AT91_PMC_V1,
  1128. },
  1129. {
  1130. .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
  1131. .mckr = 0x28,
  1132. .version = AT91_PMC_V2,
  1133. },
  1134. {
  1135. .mckr = 0x28,
  1136. .version = AT91_PMC_V2,
  1137. },
  1138. };
  1139. static const struct of_device_id atmel_pmc_ids[] __initconst = {
  1140. { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
  1141. { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
  1142. { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
  1143. { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
  1144. { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
  1145. { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
  1146. { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
  1147. { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
  1148. { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
  1149. { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
  1150. { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
  1151. { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
  1152. { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
  1153. { /* sentinel */ },
  1154. };
  1155. static void __init at91_pm_modes_validate(const int *modes, int len)
  1156. {
  1157. u8 i, standby = 0, suspend = 0;
  1158. int mode;
  1159. for (i = 0; i < len; i++) {
  1160. if (standby && suspend)
  1161. break;
  1162. if (modes[i] == soc_pm.data.standby_mode && !standby) {
  1163. standby = 1;
  1164. continue;
  1165. }
  1166. if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
  1167. suspend = 1;
  1168. continue;
  1169. }
  1170. }
  1171. if (!standby) {
  1172. if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
  1173. mode = AT91_PM_ULP0;
  1174. else
  1175. mode = AT91_PM_STANDBY;
  1176. pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
  1177. pm_modes[soc_pm.data.standby_mode].pattern,
  1178. pm_modes[mode].pattern);
  1179. soc_pm.data.standby_mode = mode;
  1180. }
  1181. if (!suspend) {
  1182. if (soc_pm.data.standby_mode == AT91_PM_ULP0)
  1183. mode = AT91_PM_STANDBY;
  1184. else
  1185. mode = AT91_PM_ULP0;
  1186. pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
  1187. pm_modes[soc_pm.data.suspend_mode].pattern,
  1188. pm_modes[mode].pattern);
  1189. soc_pm.data.suspend_mode = mode;
  1190. }
  1191. }
  1192. static void __init at91_pm_init(void (*pm_idle)(void))
  1193. {
  1194. struct device_node *pmc_np;
  1195. const struct of_device_id *of_id;
  1196. const struct pmc_info *pmc;
  1197. if (at91_cpuidle_device.dev.platform_data)
  1198. platform_device_register(&at91_cpuidle_device);
  1199. pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
  1200. soc_pm.data.pmc = of_iomap(pmc_np, 0);
  1201. of_node_put(pmc_np);
  1202. if (!soc_pm.data.pmc) {
  1203. pr_err("AT91: PM not supported, PMC not found\n");
  1204. return;
  1205. }
  1206. pmc = of_id->data;
  1207. soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
  1208. soc_pm.data.pmc_mckr_offset = pmc->mckr;
  1209. soc_pm.data.pmc_version = pmc->version;
  1210. if (pm_idle)
  1211. arm_pm_idle = pm_idle;
  1212. at91_pm_sram_init();
  1213. if (at91_suspend_sram_fn) {
  1214. suspend_set_ops(&at91_pm_ops);
  1215. pr_info("AT91: PM: standby: %s, suspend: %s\n",
  1216. pm_modes[soc_pm.data.standby_mode].pattern,
  1217. pm_modes[soc_pm.data.suspend_mode].pattern);
  1218. } else {
  1219. pr_info("AT91: PM not supported, due to no SRAM allocated\n");
  1220. }
  1221. }
  1222. void __init at91rm9200_pm_init(void)
  1223. {
  1224. int ret;
  1225. if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
  1226. return;
  1227. /*
  1228. * Force STANDBY and ULP0 mode to avoid calling
  1229. * at91_pm_modes_validate() which may increase booting time.
  1230. * Platform supports anyway only STANDBY and ULP0 modes.
  1231. */
  1232. soc_pm.data.standby_mode = AT91_PM_STANDBY;
  1233. soc_pm.data.suspend_mode = AT91_PM_ULP0;
  1234. ret = at91_dt_ramc(false);
  1235. if (ret)
  1236. return;
  1237. /*
  1238. * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
  1239. */
  1240. at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
  1241. at91_pm_init(at91rm9200_idle);
  1242. }
  1243. void __init sam9x60_pm_init(void)
  1244. {
  1245. static const int modes[] __initconst = {
  1246. AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
  1247. };
  1248. static const int iomaps[] __initconst = {
  1249. [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
  1250. };
  1251. int ret;
  1252. if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
  1253. return;
  1254. at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
  1255. at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
  1256. ret = at91_dt_ramc(false);
  1257. if (ret)
  1258. return;
  1259. at91_pm_init(NULL);
  1260. soc_pm.ws_ids = sam9x60_ws_ids;
  1261. soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
  1262. }
  1263. void __init at91sam9_pm_init(void)
  1264. {
  1265. int ret;
  1266. if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
  1267. return;
  1268. /*
  1269. * Force STANDBY and ULP0 mode to avoid calling
  1270. * at91_pm_modes_validate() which may increase booting time.
  1271. * Platform supports anyway only STANDBY and ULP0 modes.
  1272. */
  1273. soc_pm.data.standby_mode = AT91_PM_STANDBY;
  1274. soc_pm.data.suspend_mode = AT91_PM_ULP0;
  1275. ret = at91_dt_ramc(false);
  1276. if (ret)
  1277. return;
  1278. at91_pm_init(at91sam9_idle);
  1279. }
  1280. void __init sama5_pm_init(void)
  1281. {
  1282. static const int modes[] __initconst = {
  1283. AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
  1284. };
  1285. static const u32 iomaps[] __initconst = {
  1286. [AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC),
  1287. [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC),
  1288. };
  1289. int ret;
  1290. if (!IS_ENABLED(CONFIG_SOC_SAMA5))
  1291. return;
  1292. at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
  1293. at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
  1294. ret = at91_dt_ramc(false);
  1295. if (ret)
  1296. return;
  1297. at91_pm_init(NULL);
  1298. /* Quirks applies to ULP0, ULP0 fast and ULP1 modes. */
  1299. soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) |
  1300. BIT(AT91_PM_ULP0_FAST) |
  1301. BIT(AT91_PM_ULP1);
  1302. /* Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup source. */
  1303. soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) |
  1304. BIT(AT91_PM_ULP0_FAST);
  1305. }
  1306. void __init sama5d2_pm_init(void)
  1307. {
  1308. static const int modes[] __initconst = {
  1309. AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
  1310. AT91_PM_BACKUP,
  1311. };
  1312. static const u32 iomaps[] __initconst = {
  1313. [AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC),
  1314. [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC),
  1315. [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC) |
  1316. AT91_PM_IOMAP(ETHC),
  1317. [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) |
  1318. AT91_PM_IOMAP(SFRBU),
  1319. };
  1320. int ret;
  1321. if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
  1322. return;
  1323. if (IS_ENABLED(CONFIG_ATMEL_SECURE_PM)) {
  1324. pr_warn("AT91: Secure PM: ignoring standby mode\n");
  1325. at91_pm_secure_init();
  1326. return;
  1327. }
  1328. at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
  1329. at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
  1330. ret = at91_dt_ramc(false);
  1331. if (ret)
  1332. return;
  1333. at91_pm_init(NULL);
  1334. soc_pm.ws_ids = sama5d2_ws_ids;
  1335. soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
  1336. soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
  1337. soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
  1338. soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
  1339. soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
  1340. soc_pm.sfrbu_regs.pswbu.state = BIT(3);
  1341. /* Quirk applies to ULP0, ULP0 fast and ULP1 modes. */
  1342. soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) |
  1343. BIT(AT91_PM_ULP0_FAST) |
  1344. BIT(AT91_PM_ULP1);
  1345. /*
  1346. * Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup
  1347. * source.
  1348. */
  1349. soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) |
  1350. BIT(AT91_PM_ULP0_FAST);
  1351. }
  1352. void __init sama7_pm_init(void)
  1353. {
  1354. static const int modes[] __initconst = {
  1355. AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
  1356. };
  1357. static const u32 iomaps[] __initconst = {
  1358. [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU),
  1359. [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
  1360. AT91_PM_IOMAP(SHDWC) |
  1361. AT91_PM_IOMAP(ETHC),
  1362. [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) |
  1363. AT91_PM_IOMAP(SHDWC),
  1364. };
  1365. int ret;
  1366. if (!IS_ENABLED(CONFIG_SOC_SAMA7))
  1367. return;
  1368. at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
  1369. ret = at91_dt_ramc(true);
  1370. if (ret)
  1371. return;
  1372. at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
  1373. at91_pm_init(NULL);
  1374. soc_pm.ws_ids = sama7g5_ws_ids;
  1375. soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
  1376. soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
  1377. soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
  1378. soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
  1379. soc_pm.sfrbu_regs.pswbu.state = BIT(2);
  1380. /* Quirks applies to ULP1 for both Ethernet interfaces. */
  1381. soc_pm.quirks.eth[AT91_PM_E_ETH].modes = BIT(AT91_PM_ULP1);
  1382. soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP1);
  1383. }
  1384. static int __init at91_pm_modes_select(char *str)
  1385. {
  1386. char *s;
  1387. substring_t args[MAX_OPT_ARGS];
  1388. int standby, suspend;
  1389. if (!str)
  1390. return 0;
  1391. s = strsep(&str, ",");
  1392. standby = match_token(s, pm_modes, args);
  1393. if (standby < 0)
  1394. return 0;
  1395. suspend = match_token(str, pm_modes, args);
  1396. if (suspend < 0)
  1397. return 0;
  1398. soc_pm.data.standby_mode = standby;
  1399. soc_pm.data.suspend_mode = suspend;
  1400. return 0;
  1401. }
  1402. early_param("atmel.pm_modes", at91_pm_modes_select);