smp_scu.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/kernel/smp_scu.c
  4. *
  5. * Copyright (C) 2002 ARM Ltd.
  6. * All Rights Reserved
  7. */
  8. #include <linux/init.h>
  9. #include <linux/io.h>
  10. #include <asm/smp_plat.h>
  11. #include <asm/smp_scu.h>
  12. #include <asm/cacheflush.h>
  13. #include <asm/cputype.h>
  14. #define SCU_CTRL 0x00
  15. #define SCU_ENABLE (1 << 0)
  16. #define SCU_STANDBY_ENABLE (1 << 5)
  17. #define SCU_CONFIG 0x04
  18. #define SCU_CPU_STATUS 0x08
  19. #define SCU_CPU_STATUS_MASK GENMASK(1, 0)
  20. #define SCU_INVALIDATE 0x0c
  21. #define SCU_FPGA_REVISION 0x10
  22. #ifdef CONFIG_SMP
  23. /*
  24. * Get the number of CPU cores from the SCU configuration
  25. */
  26. unsigned int __init scu_get_core_count(void __iomem *scu_base)
  27. {
  28. unsigned int ncores = readl_relaxed(scu_base + SCU_CONFIG);
  29. return (ncores & 0x03) + 1;
  30. }
  31. /*
  32. * Enable the SCU
  33. */
  34. void scu_enable(void __iomem *scu_base)
  35. {
  36. u32 scu_ctrl;
  37. #ifdef CONFIG_ARM_ERRATA_764369
  38. /* Cortex-A9 only */
  39. if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc090) {
  40. scu_ctrl = readl_relaxed(scu_base + 0x30);
  41. if (!(scu_ctrl & 1))
  42. writel_relaxed(scu_ctrl | 0x1, scu_base + 0x30);
  43. }
  44. #endif
  45. scu_ctrl = readl_relaxed(scu_base + SCU_CTRL);
  46. /* already enabled? */
  47. if (scu_ctrl & SCU_ENABLE)
  48. return;
  49. scu_ctrl |= SCU_ENABLE;
  50. /* Cortex-A9 earlier than r2p0 has no standby bit in SCU */
  51. if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc090 &&
  52. (read_cpuid_id() & 0x00f0000f) >= 0x00200000)
  53. scu_ctrl |= SCU_STANDBY_ENABLE;
  54. writel_relaxed(scu_ctrl, scu_base + SCU_CTRL);
  55. /*
  56. * Ensure that the data accessed by CPU0 before the SCU was
  57. * initialised is visible to the other CPUs.
  58. */
  59. flush_cache_all();
  60. }
  61. #endif
  62. static int scu_set_power_mode_internal(void __iomem *scu_base,
  63. unsigned int logical_cpu,
  64. unsigned int mode)
  65. {
  66. unsigned int val;
  67. int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0);
  68. if (mode > 3 || mode == 1 || cpu > 3)
  69. return -EINVAL;
  70. val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
  71. val &= ~SCU_CPU_STATUS_MASK;
  72. val |= mode;
  73. writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
  74. return 0;
  75. }
  76. /*
  77. * Set the executing CPUs power mode as defined. This will be in
  78. * preparation for it executing a WFI instruction.
  79. *
  80. * This function must be called with preemption disabled, and as it
  81. * has the side effect of disabling coherency, caches must have been
  82. * flushed. Interrupts must also have been disabled.
  83. */
  84. int scu_power_mode(void __iomem *scu_base, unsigned int mode)
  85. {
  86. return scu_set_power_mode_internal(scu_base, smp_processor_id(), mode);
  87. }
  88. /*
  89. * Set the given (logical) CPU's power mode to SCU_PM_NORMAL.
  90. */
  91. int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu)
  92. {
  93. return scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL);
  94. }
  95. int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu)
  96. {
  97. unsigned int val;
  98. int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0);
  99. if (cpu > 3)
  100. return -EINVAL;
  101. val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
  102. val &= SCU_CPU_STATUS_MASK;
  103. return val;
  104. }