iwmmxt.S 8.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * linux/arch/arm/kernel/iwmmxt.S
  4. *
  5. * XScale iWMMXt (Concan) context switching and handling
  6. *
  7. * Initial code:
  8. * Copyright (c) 2003, Intel Corporation
  9. *
  10. * Full lazy switching support, optimizations and more, by Nicolas Pitre
  11. * Copyright (c) 2003-2004, MontaVista Software, Inc.
  12. */
  13. #include <linux/linkage.h>
  14. #include <asm/ptrace.h>
  15. #include <asm/thread_info.h>
  16. #include <asm/asm-offsets.h>
  17. #include <asm/assembler.h>
  18. #include "iwmmxt.h"
  19. #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
  20. #define PJ4(code...) code
  21. #define XSC(code...)
  22. #elif defined(CONFIG_CPU_MOHAWK) || \
  23. defined(CONFIG_CPU_XSC3) || \
  24. defined(CONFIG_CPU_XSCALE)
  25. #define PJ4(code...)
  26. #define XSC(code...) code
  27. #else
  28. #error "Unsupported iWMMXt architecture"
  29. #endif
  30. #define MMX_WR0 (0x00)
  31. #define MMX_WR1 (0x08)
  32. #define MMX_WR2 (0x10)
  33. #define MMX_WR3 (0x18)
  34. #define MMX_WR4 (0x20)
  35. #define MMX_WR5 (0x28)
  36. #define MMX_WR6 (0x30)
  37. #define MMX_WR7 (0x38)
  38. #define MMX_WR8 (0x40)
  39. #define MMX_WR9 (0x48)
  40. #define MMX_WR10 (0x50)
  41. #define MMX_WR11 (0x58)
  42. #define MMX_WR12 (0x60)
  43. #define MMX_WR13 (0x68)
  44. #define MMX_WR14 (0x70)
  45. #define MMX_WR15 (0x78)
  46. #define MMX_WCSSF (0x80)
  47. #define MMX_WCASF (0x84)
  48. #define MMX_WCGR0 (0x88)
  49. #define MMX_WCGR1 (0x8C)
  50. #define MMX_WCGR2 (0x90)
  51. #define MMX_WCGR3 (0x94)
  52. #define MMX_SIZE (0x98)
  53. .text
  54. .arm
  55. /*
  56. * Lazy switching of Concan coprocessor context
  57. *
  58. * r10 = struct thread_info pointer
  59. * r9 = ret_from_exception
  60. * lr = undefined instr exit
  61. *
  62. * called from prefetch exception handler with interrupts enabled
  63. */
  64. ENTRY(iwmmxt_task_enable)
  65. inc_preempt_count r10, r3
  66. XSC(mrc p15, 0, r2, c15, c1, 0)
  67. PJ4(mrc p15, 0, r2, c1, c0, 2)
  68. @ CP0 and CP1 accessible?
  69. XSC(tst r2, #0x3)
  70. PJ4(tst r2, #0xf)
  71. bne 4f @ if so no business here
  72. @ enable access to CP0 and CP1
  73. XSC(orr r2, r2, #0x3)
  74. XSC(mcr p15, 0, r2, c15, c1, 0)
  75. PJ4(orr r2, r2, #0xf)
  76. PJ4(mcr p15, 0, r2, c1, c0, 2)
  77. ldr r3, =concan_owner
  78. add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area
  79. ldr r2, [sp, #60] @ current task pc value
  80. ldr r1, [r3] @ get current Concan owner
  81. str r0, [r3] @ this task now owns Concan regs
  82. sub r2, r2, #4 @ adjust pc back
  83. str r2, [sp, #60]
  84. mrc p15, 0, r2, c2, c0, 0
  85. mov r2, r2 @ cpwait
  86. bl concan_save
  87. #ifdef CONFIG_PREEMPT_COUNT
  88. get_thread_info r10
  89. #endif
  90. 4: dec_preempt_count r10, r3
  91. ret r9 @ normal exit from exception
  92. concan_save:
  93. teq r1, #0 @ test for last ownership
  94. beq concan_load @ no owner, skip save
  95. tmrc r2, wCon
  96. @ CUP? wCx
  97. tst r2, #0x1
  98. beq 1f
  99. concan_dump:
  100. wstrw wCSSF, r1, MMX_WCSSF
  101. wstrw wCASF, r1, MMX_WCASF
  102. wstrw wCGR0, r1, MMX_WCGR0
  103. wstrw wCGR1, r1, MMX_WCGR1
  104. wstrw wCGR2, r1, MMX_WCGR2
  105. wstrw wCGR3, r1, MMX_WCGR3
  106. 1: @ MUP? wRn
  107. tst r2, #0x2
  108. beq 2f
  109. wstrd wR0, r1, MMX_WR0
  110. wstrd wR1, r1, MMX_WR1
  111. wstrd wR2, r1, MMX_WR2
  112. wstrd wR3, r1, MMX_WR3
  113. wstrd wR4, r1, MMX_WR4
  114. wstrd wR5, r1, MMX_WR5
  115. wstrd wR6, r1, MMX_WR6
  116. wstrd wR7, r1, MMX_WR7
  117. wstrd wR8, r1, MMX_WR8
  118. wstrd wR9, r1, MMX_WR9
  119. wstrd wR10, r1, MMX_WR10
  120. wstrd wR11, r1, MMX_WR11
  121. wstrd wR12, r1, MMX_WR12
  122. wstrd wR13, r1, MMX_WR13
  123. wstrd wR14, r1, MMX_WR14
  124. wstrd wR15, r1, MMX_WR15
  125. 2: teq r0, #0 @ anything to load?
  126. reteq lr @ if not, return
  127. concan_load:
  128. @ Load wRn
  129. wldrd wR0, r0, MMX_WR0
  130. wldrd wR1, r0, MMX_WR1
  131. wldrd wR2, r0, MMX_WR2
  132. wldrd wR3, r0, MMX_WR3
  133. wldrd wR4, r0, MMX_WR4
  134. wldrd wR5, r0, MMX_WR5
  135. wldrd wR6, r0, MMX_WR6
  136. wldrd wR7, r0, MMX_WR7
  137. wldrd wR8, r0, MMX_WR8
  138. wldrd wR9, r0, MMX_WR9
  139. wldrd wR10, r0, MMX_WR10
  140. wldrd wR11, r0, MMX_WR11
  141. wldrd wR12, r0, MMX_WR12
  142. wldrd wR13, r0, MMX_WR13
  143. wldrd wR14, r0, MMX_WR14
  144. wldrd wR15, r0, MMX_WR15
  145. @ Load wCx
  146. wldrw wCSSF, r0, MMX_WCSSF
  147. wldrw wCASF, r0, MMX_WCASF
  148. wldrw wCGR0, r0, MMX_WCGR0
  149. wldrw wCGR1, r0, MMX_WCGR1
  150. wldrw wCGR2, r0, MMX_WCGR2
  151. wldrw wCGR3, r0, MMX_WCGR3
  152. @ clear CUP/MUP (only if r1 != 0)
  153. teq r1, #0
  154. mov r2, #0
  155. reteq lr
  156. tmcr wCon, r2
  157. ret lr
  158. ENDPROC(iwmmxt_task_enable)
  159. /*
  160. * Back up Concan regs to save area and disable access to them
  161. * (mainly for gdb or sleep mode usage)
  162. *
  163. * r0 = struct thread_info pointer of target task or NULL for any
  164. */
  165. ENTRY(iwmmxt_task_disable)
  166. stmfd sp!, {r4, lr}
  167. mrs ip, cpsr
  168. orr r2, ip, #PSR_I_BIT @ disable interrupts
  169. msr cpsr_c, r2
  170. ldr r3, =concan_owner
  171. add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
  172. ldr r1, [r3] @ get current Concan owner
  173. teq r1, #0 @ any current owner?
  174. beq 1f @ no: quit
  175. teq r0, #0 @ any owner?
  176. teqne r1, r2 @ or specified one?
  177. bne 1f @ no: quit
  178. @ enable access to CP0 and CP1
  179. XSC(mrc p15, 0, r4, c15, c1, 0)
  180. XSC(orr r4, r4, #0x3)
  181. XSC(mcr p15, 0, r4, c15, c1, 0)
  182. PJ4(mrc p15, 0, r4, c1, c0, 2)
  183. PJ4(orr r4, r4, #0xf)
  184. PJ4(mcr p15, 0, r4, c1, c0, 2)
  185. mov r0, #0 @ nothing to load
  186. str r0, [r3] @ no more current owner
  187. mrc p15, 0, r2, c2, c0, 0
  188. mov r2, r2 @ cpwait
  189. bl concan_save
  190. @ disable access to CP0 and CP1
  191. XSC(bic r4, r4, #0x3)
  192. XSC(mcr p15, 0, r4, c15, c1, 0)
  193. PJ4(bic r4, r4, #0xf)
  194. PJ4(mcr p15, 0, r4, c1, c0, 2)
  195. mrc p15, 0, r2, c2, c0, 0
  196. mov r2, r2 @ cpwait
  197. 1: msr cpsr_c, ip @ restore interrupt mode
  198. ldmfd sp!, {r4, pc}
  199. ENDPROC(iwmmxt_task_disable)
  200. /*
  201. * Copy Concan state to given memory address
  202. *
  203. * r0 = struct thread_info pointer of target task
  204. * r1 = memory address where to store Concan state
  205. *
  206. * this is called mainly in the creation of signal stack frames
  207. */
  208. ENTRY(iwmmxt_task_copy)
  209. mrs ip, cpsr
  210. orr r2, ip, #PSR_I_BIT @ disable interrupts
  211. msr cpsr_c, r2
  212. ldr r3, =concan_owner
  213. add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
  214. ldr r3, [r3] @ get current Concan owner
  215. teq r2, r3 @ does this task own it...
  216. beq 1f
  217. @ current Concan values are in the task save area
  218. msr cpsr_c, ip @ restore interrupt mode
  219. mov r0, r1
  220. mov r1, r2
  221. mov r2, #MMX_SIZE
  222. b memcpy
  223. 1: @ this task owns Concan regs -- grab a copy from there
  224. mov r0, #0 @ nothing to load
  225. mov r2, #3 @ save all regs
  226. mov r3, lr @ preserve return address
  227. bl concan_dump
  228. msr cpsr_c, ip @ restore interrupt mode
  229. ret r3
  230. ENDPROC(iwmmxt_task_copy)
  231. /*
  232. * Restore Concan state from given memory address
  233. *
  234. * r0 = struct thread_info pointer of target task
  235. * r1 = memory address where to get Concan state from
  236. *
  237. * this is used to restore Concan state when unwinding a signal stack frame
  238. */
  239. ENTRY(iwmmxt_task_restore)
  240. mrs ip, cpsr
  241. orr r2, ip, #PSR_I_BIT @ disable interrupts
  242. msr cpsr_c, r2
  243. ldr r3, =concan_owner
  244. add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
  245. ldr r3, [r3] @ get current Concan owner
  246. bic r2, r2, #0x7 @ 64-bit alignment
  247. teq r2, r3 @ does this task own it...
  248. beq 1f
  249. @ this task doesn't own Concan regs -- use its save area
  250. msr cpsr_c, ip @ restore interrupt mode
  251. mov r0, r2
  252. mov r2, #MMX_SIZE
  253. b memcpy
  254. 1: @ this task owns Concan regs -- load them directly
  255. mov r0, r1
  256. mov r1, #0 @ don't clear CUP/MUP
  257. mov r3, lr @ preserve return address
  258. bl concan_load
  259. msr cpsr_c, ip @ restore interrupt mode
  260. ret r3
  261. ENDPROC(iwmmxt_task_restore)
  262. /*
  263. * Concan handling on task switch
  264. *
  265. * r0 = next thread_info pointer
  266. *
  267. * Called only from the iwmmxt notifier with task preemption disabled.
  268. */
  269. ENTRY(iwmmxt_task_switch)
  270. XSC(mrc p15, 0, r1, c15, c1, 0)
  271. PJ4(mrc p15, 0, r1, c1, c0, 2)
  272. @ CP0 and CP1 accessible?
  273. XSC(tst r1, #0x3)
  274. PJ4(tst r1, #0xf)
  275. bne 1f @ yes: block them for next task
  276. ldr r2, =concan_owner
  277. add r3, r0, #TI_IWMMXT_STATE @ get next task Concan save area
  278. ldr r2, [r2] @ get current Concan owner
  279. teq r2, r3 @ next task owns it?
  280. retne lr @ no: leave Concan disabled
  281. 1: @ flip Concan access
  282. XSC(eor r1, r1, #0x3)
  283. XSC(mcr p15, 0, r1, c15, c1, 0)
  284. PJ4(eor r1, r1, #0xf)
  285. PJ4(mcr p15, 0, r1, c1, c0, 2)
  286. mrc p15, 0, r1, c2, c0, 0
  287. sub pc, lr, r1, lsr #32 @ cpwait and return
  288. ENDPROC(iwmmxt_task_switch)
  289. /*
  290. * Remove Concan ownership of given task
  291. *
  292. * r0 = struct thread_info pointer
  293. */
  294. ENTRY(iwmmxt_task_release)
  295. mrs r2, cpsr
  296. orr ip, r2, #PSR_I_BIT @ disable interrupts
  297. msr cpsr_c, ip
  298. ldr r3, =concan_owner
  299. add r0, r0, #TI_IWMMXT_STATE @ get task Concan save area
  300. ldr r1, [r3] @ get current Concan owner
  301. eors r0, r0, r1 @ if equal...
  302. streq r0, [r3] @ then clear ownership
  303. msr cpsr_c, r2 @ restore interrupts
  304. ret lr
  305. ENDPROC(iwmmxt_task_release)
  306. .data
  307. .align 2
  308. concan_owner:
  309. .word 0