hyp-stub.S 5.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright (c) 2012 Linaro Limited.
  4. */
  5. #include <linux/init.h>
  6. #include <linux/irqchip/arm-gic-v3.h>
  7. #include <linux/linkage.h>
  8. #include <asm/assembler.h>
  9. #include <asm/virt.h>
  10. #ifndef ZIMAGE
  11. /*
  12. * For the kernel proper, we need to find out the CPU boot mode long after
  13. * boot, so we need to store it in a writable variable.
  14. *
  15. * This is not in .bss, because we set it sufficiently early that the boot-time
  16. * zeroing of .bss would clobber it.
  17. */
  18. .data
  19. .align 2
  20. ENTRY(__boot_cpu_mode)
  21. .long 0
  22. .text
  23. /*
  24. * Save the primary CPU boot mode. Requires 2 scratch registers.
  25. */
  26. .macro store_primary_cpu_mode reg1, reg2
  27. mrs \reg1, cpsr
  28. and \reg1, \reg1, #MODE_MASK
  29. str_l \reg1, __boot_cpu_mode, \reg2
  30. .endm
  31. /*
  32. * Compare the current mode with the one saved on the primary CPU.
  33. * If they don't match, record that fact. The Z bit indicates
  34. * if there's a match or not.
  35. * Requires 2 additional scratch registers.
  36. */
  37. .macro compare_cpu_mode_with_primary mode, reg1, reg2
  38. adr_l \reg2, __boot_cpu_mode
  39. ldr \reg1, [\reg2]
  40. cmp \mode, \reg1 @ matches primary CPU boot mode?
  41. orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
  42. strne \reg1, [\reg2] @ record what happened and give up
  43. .endm
  44. #else /* ZIMAGE */
  45. .macro store_primary_cpu_mode reg1:req, reg2:req
  46. .endm
  47. /*
  48. * The zImage loader only runs on one CPU, so we don't bother with mult-CPU
  49. * consistency checking:
  50. */
  51. .macro compare_cpu_mode_with_primary mode, reg1, reg2
  52. cmp \mode, \mode
  53. .endm
  54. #endif /* ZIMAGE */
  55. /*
  56. * Hypervisor stub installation functions.
  57. *
  58. * These must be called with the MMU and D-cache off.
  59. * They are not ABI compliant and are only intended to be called from the kernel
  60. * entry points in head.S.
  61. */
  62. @ Call this from the primary CPU
  63. ENTRY(__hyp_stub_install)
  64. store_primary_cpu_mode r4, r5
  65. ENDPROC(__hyp_stub_install)
  66. @ fall through...
  67. @ Secondary CPUs should call here
  68. ENTRY(__hyp_stub_install_secondary)
  69. mrs r4, cpsr
  70. and r4, r4, #MODE_MASK
  71. /*
  72. * If the secondary has booted with a different mode, give up
  73. * immediately.
  74. */
  75. compare_cpu_mode_with_primary r4, r5, r6
  76. retne lr
  77. /*
  78. * Once we have given up on one CPU, we do not try to install the
  79. * stub hypervisor on the remaining ones: because the saved boot mode
  80. * is modified, it can't compare equal to the CPSR mode field any
  81. * more.
  82. *
  83. * Otherwise...
  84. */
  85. cmp r4, #HYP_MODE
  86. retne lr @ give up if the CPU is not in HYP mode
  87. /*
  88. * Configure HSCTLR to set correct exception endianness/instruction set
  89. * state etc.
  90. * Turn off all traps
  91. * Eventually, CPU-specific code might be needed -- assume not for now
  92. *
  93. * This code relies on the "eret" instruction to synchronize the
  94. * various coprocessor accesses. This is done when we switch to SVC
  95. * (see safe_svcmode_maskall).
  96. */
  97. @ Now install the hypervisor stub:
  98. W(adr) r7, __hyp_stub_vectors
  99. mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
  100. @ Disable all traps, so we don't get any nasty surprise
  101. mov r7, #0
  102. mcr p15, 4, r7, c1, c1, 0 @ HCR
  103. mcr p15, 4, r7, c1, c1, 2 @ HCPTR
  104. mcr p15, 4, r7, c1, c1, 3 @ HSTR
  105. THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
  106. ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE
  107. mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
  108. mrc p15, 4, r7, c1, c1, 1 @ HDCR
  109. and r7, #0x1f @ Preserve HPMN
  110. mcr p15, 4, r7, c1, c1, 1 @ HDCR
  111. @ Make sure NS-SVC is initialised appropriately
  112. mrc p15, 0, r7, c1, c0, 0 @ SCTLR
  113. orr r7, #(1 << 5) @ CP15 barriers enabled
  114. bic r7, #(3 << 7) @ Clear SED/ITD for v8 (RES0 for v7)
  115. bic r7, #(3 << 19) @ WXN and UWXN disabled
  116. mcr p15, 0, r7, c1, c0, 0 @ SCTLR
  117. mrc p15, 0, r7, c0, c0, 0 @ MIDR
  118. mcr p15, 4, r7, c0, c0, 0 @ VPIDR
  119. mrc p15, 0, r7, c0, c0, 5 @ MPIDR
  120. mcr p15, 4, r7, c0, c0, 5 @ VMPIDR
  121. #if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER)
  122. @ make CNTP_* and CNTPCT accessible from PL1
  123. mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
  124. ubfx r7, r7, #16, #4
  125. teq r7, #0
  126. beq 1f
  127. mrc p15, 4, r7, c14, c1, 0 @ CNTHCTL
  128. orr r7, r7, #3 @ PL1PCEN | PL1PCTEN
  129. mcr p15, 4, r7, c14, c1, 0 @ CNTHCTL
  130. mov r7, #0
  131. mcrr p15, 4, r7, r7, c14 @ CNTVOFF
  132. @ Disable virtual timer in case it was counting
  133. mrc p15, 0, r7, c14, c3, 1 @ CNTV_CTL
  134. bic r7, #1 @ Clear ENABLE
  135. mcr p15, 0, r7, c14, c3, 1 @ CNTV_CTL
  136. 1:
  137. #endif
  138. #ifdef CONFIG_ARM_GIC_V3
  139. @ Check whether GICv3 system registers are available
  140. mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
  141. ubfx r7, r7, #28, #4
  142. teq r7, #0
  143. beq 2f
  144. @ Enable system register accesses
  145. mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
  146. orr r7, r7, #(ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE)
  147. mcr p15, 4, r7, c12, c9, 5 @ ICC_HSRE
  148. isb
  149. @ SRE bit could be forced to 0 by firmware.
  150. @ Check whether it sticks before accessing any other sysreg
  151. mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
  152. tst r7, #ICC_SRE_EL2_SRE
  153. beq 2f
  154. mov r7, #0
  155. mcr p15, 4, r7, c12, c11, 0 @ ICH_HCR
  156. 2:
  157. #endif
  158. bx lr @ The boot CPU mode is left in r4.
  159. ENDPROC(__hyp_stub_install_secondary)
  160. __hyp_stub_do_trap:
  161. #ifdef ZIMAGE
  162. teq r0, #HVC_SET_VECTORS
  163. bne 1f
  164. /* Only the ZIMAGE stubs can change the HYP vectors */
  165. mcr p15, 4, r1, c12, c0, 0 @ set HVBAR
  166. b __hyp_stub_exit
  167. #endif
  168. 1: teq r0, #HVC_SOFT_RESTART
  169. bne 2f
  170. bx r1
  171. 2: ldr r0, =HVC_STUB_ERR
  172. __ERET
  173. __hyp_stub_exit:
  174. mov r0, #0
  175. __ERET
  176. ENDPROC(__hyp_stub_do_trap)
  177. /*
  178. * __hyp_set_vectors is only used when ZIMAGE must bounce between HYP
  179. * and SVC. For the kernel itself, the vectors are set once and for
  180. * all by the stubs.
  181. */
  182. ENTRY(__hyp_set_vectors)
  183. mov r1, r0
  184. mov r0, #HVC_SET_VECTORS
  185. __HVC(0)
  186. ret lr
  187. ENDPROC(__hyp_set_vectors)
  188. ENTRY(__hyp_soft_restart)
  189. mov r1, r0
  190. mov r0, #HVC_SOFT_RESTART
  191. __HVC(0)
  192. ret lr
  193. ENDPROC(__hyp_soft_restart)
  194. .align 5
  195. ENTRY(__hyp_stub_vectors)
  196. __hyp_stub_reset: W(b) .
  197. __hyp_stub_und: W(b) .
  198. __hyp_stub_svc: W(b) .
  199. __hyp_stub_pabort: W(b) .
  200. __hyp_stub_dabort: W(b) .
  201. __hyp_stub_trap: W(b) __hyp_stub_do_trap
  202. __hyp_stub_irq: W(b) .
  203. __hyp_stub_fiq: W(b) .
  204. ENDPROC(__hyp_stub_vectors)