bios32.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * linux/arch/arm/kernel/bios32.c
  4. *
  5. * PCI bios-type initialisation for PCI machines
  6. *
  7. * Bits taken from various places.
  8. */
  9. #include <linux/export.h>
  10. #include <linux/kernel.h>
  11. #include <linux/pci.h>
  12. #include <linux/slab.h>
  13. #include <linux/init.h>
  14. #include <linux/io.h>
  15. #include <asm/mach-types.h>
  16. #include <asm/mach/map.h>
  17. #include <asm/mach/pci.h>
  18. static int debug_pci;
  19. /*
  20. * We can't use pci_get_device() here since we are
  21. * called from interrupt context.
  22. */
  23. static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
  24. {
  25. struct pci_dev *dev;
  26. list_for_each_entry(dev, &bus->devices, bus_list) {
  27. u16 status;
  28. /*
  29. * ignore host bridge - we handle
  30. * that separately
  31. */
  32. if (dev->bus->number == 0 && dev->devfn == 0)
  33. continue;
  34. pci_read_config_word(dev, PCI_STATUS, &status);
  35. if (status == 0xffff)
  36. continue;
  37. if ((status & status_mask) == 0)
  38. continue;
  39. /* clear the status errors */
  40. pci_write_config_word(dev, PCI_STATUS, status & status_mask);
  41. if (warn)
  42. printk("(%s: %04X) ", pci_name(dev), status);
  43. }
  44. list_for_each_entry(dev, &bus->devices, bus_list)
  45. if (dev->subordinate)
  46. pcibios_bus_report_status(dev->subordinate, status_mask, warn);
  47. }
  48. void pcibios_report_status(u_int status_mask, int warn)
  49. {
  50. struct pci_bus *bus;
  51. list_for_each_entry(bus, &pci_root_buses, node)
  52. pcibios_bus_report_status(bus, status_mask, warn);
  53. }
  54. /*
  55. * We don't use this to fix the device, but initialisation of it.
  56. * It's not the correct use for this, but it works.
  57. * Note that the arbiter/ISA bridge appears to be buggy, specifically in
  58. * the following area:
  59. * 1. park on CPU
  60. * 2. ISA bridge ping-pong
  61. * 3. ISA bridge master handling of target RETRY
  62. *
  63. * Bug 3 is responsible for the sound DMA grinding to a halt. We now
  64. * live with bug 2.
  65. */
  66. static void pci_fixup_83c553(struct pci_dev *dev)
  67. {
  68. /*
  69. * Set memory region to start at address 0, and enable IO
  70. */
  71. pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
  72. pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
  73. dev->resource[0].end -= dev->resource[0].start;
  74. dev->resource[0].start = 0;
  75. /*
  76. * All memory requests from ISA to be channelled to PCI
  77. */
  78. pci_write_config_byte(dev, 0x48, 0xff);
  79. /*
  80. * Enable ping-pong on bus master to ISA bridge transactions.
  81. * This improves the sound DMA substantially. The fixed
  82. * priority arbiter also helps (see below).
  83. */
  84. pci_write_config_byte(dev, 0x42, 0x01);
  85. /*
  86. * Enable PCI retry
  87. */
  88. pci_write_config_byte(dev, 0x40, 0x22);
  89. /*
  90. * We used to set the arbiter to "park on last master" (bit
  91. * 1 set), but unfortunately the CyberPro does not park the
  92. * bus. We must therefore park on CPU. Unfortunately, this
  93. * may trigger yet another bug in the 553.
  94. */
  95. pci_write_config_byte(dev, 0x83, 0x02);
  96. /*
  97. * Make the ISA DMA request lowest priority, and disable
  98. * rotating priorities completely.
  99. */
  100. pci_write_config_byte(dev, 0x80, 0x11);
  101. pci_write_config_byte(dev, 0x81, 0x00);
  102. /*
  103. * Route INTA input to IRQ 11, and set IRQ11 to be level
  104. * sensitive.
  105. */
  106. pci_write_config_word(dev, 0x44, 0xb000);
  107. outb(0x08, 0x4d1);
  108. }
  109. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
  110. static void pci_fixup_unassign(struct pci_dev *dev)
  111. {
  112. dev->resource[0].end -= dev->resource[0].start;
  113. dev->resource[0].start = 0;
  114. }
  115. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
  116. /*
  117. * Prevent the PCI layer from seeing the resources allocated to this device
  118. * if it is the host bridge by marking it as such. These resources are of
  119. * no consequence to the PCI layer (they are handled elsewhere).
  120. */
  121. static void pci_fixup_dec21285(struct pci_dev *dev)
  122. {
  123. int i;
  124. if (dev->devfn == 0) {
  125. dev->class &= 0xff;
  126. dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
  127. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  128. dev->resource[i].start = 0;
  129. dev->resource[i].end = 0;
  130. dev->resource[i].flags = 0;
  131. }
  132. }
  133. }
  134. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
  135. /*
  136. * PCI IDE controllers use non-standard I/O port decoding, respect it.
  137. */
  138. static void pci_fixup_ide_bases(struct pci_dev *dev)
  139. {
  140. struct resource *r;
  141. int i;
  142. if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
  143. return;
  144. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  145. r = dev->resource + i;
  146. if ((r->start & ~0x80) == 0x374) {
  147. r->start |= 2;
  148. r->end = r->start;
  149. }
  150. }
  151. }
  152. DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
  153. /*
  154. * Put the DEC21142 to sleep
  155. */
  156. static void pci_fixup_dec21142(struct pci_dev *dev)
  157. {
  158. pci_write_config_dword(dev, 0x40, 0x80000000);
  159. }
  160. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
  161. /*
  162. * The CY82C693 needs some rather major fixups to ensure that it does
  163. * the right thing. Idea from the Alpha people, with a few additions.
  164. *
  165. * We ensure that the IDE base registers are set to 1f0/3f4 for the
  166. * primary bus, and 170/374 for the secondary bus. Also, hide them
  167. * from the PCI subsystem view as well so we won't try to perform
  168. * our own auto-configuration on them.
  169. *
  170. * In addition, we ensure that the PCI IDE interrupts are routed to
  171. * IRQ 14 and IRQ 15 respectively.
  172. *
  173. * The above gets us to a point where the IDE on this device is
  174. * functional. However, The CY82C693U _does not work_ in bus
  175. * master mode without locking the PCI bus solid.
  176. */
  177. static void pci_fixup_cy82c693(struct pci_dev *dev)
  178. {
  179. if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
  180. u32 base0, base1;
  181. if (dev->class & 0x80) { /* primary */
  182. base0 = 0x1f0;
  183. base1 = 0x3f4;
  184. } else { /* secondary */
  185. base0 = 0x170;
  186. base1 = 0x374;
  187. }
  188. pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
  189. base0 | PCI_BASE_ADDRESS_SPACE_IO);
  190. pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
  191. base1 | PCI_BASE_ADDRESS_SPACE_IO);
  192. dev->resource[0].start = 0;
  193. dev->resource[0].end = 0;
  194. dev->resource[0].flags = 0;
  195. dev->resource[1].start = 0;
  196. dev->resource[1].end = 0;
  197. dev->resource[1].flags = 0;
  198. } else if (PCI_FUNC(dev->devfn) == 0) {
  199. /*
  200. * Setup IDE IRQ routing.
  201. */
  202. pci_write_config_byte(dev, 0x4b, 14);
  203. pci_write_config_byte(dev, 0x4c, 15);
  204. /*
  205. * Disable FREQACK handshake, enable USB.
  206. */
  207. pci_write_config_byte(dev, 0x4d, 0x41);
  208. /*
  209. * Enable PCI retry, and PCI post-write buffer.
  210. */
  211. pci_write_config_byte(dev, 0x44, 0x17);
  212. /*
  213. * Enable ISA master and DMA post write buffering.
  214. */
  215. pci_write_config_byte(dev, 0x45, 0x03);
  216. }
  217. }
  218. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
  219. /*
  220. * If the bus contains any of these devices, then we must not turn on
  221. * parity checking of any kind. Currently this is CyberPro 20x0 only.
  222. */
  223. static inline int pdev_bad_for_parity(struct pci_dev *dev)
  224. {
  225. return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
  226. (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
  227. dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
  228. (dev->vendor == PCI_VENDOR_ID_ITE &&
  229. dev->device == PCI_DEVICE_ID_ITE_8152));
  230. }
  231. /*
  232. * pcibios_fixup_bus - Called after each bus is probed,
  233. * but before its children are examined.
  234. */
  235. void pcibios_fixup_bus(struct pci_bus *bus)
  236. {
  237. struct pci_dev *dev;
  238. u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
  239. /*
  240. * Walk the devices on this bus, working out what we can
  241. * and can't support.
  242. */
  243. list_for_each_entry(dev, &bus->devices, bus_list) {
  244. u16 status;
  245. pci_read_config_word(dev, PCI_STATUS, &status);
  246. /*
  247. * If any device on this bus does not support fast back
  248. * to back transfers, then the bus as a whole is not able
  249. * to support them. Having fast back to back transfers
  250. * on saves us one PCI cycle per transaction.
  251. */
  252. if (!(status & PCI_STATUS_FAST_BACK))
  253. features &= ~PCI_COMMAND_FAST_BACK;
  254. if (pdev_bad_for_parity(dev))
  255. features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
  256. switch (dev->class >> 8) {
  257. case PCI_CLASS_BRIDGE_PCI:
  258. pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
  259. status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
  260. status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
  261. pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
  262. break;
  263. case PCI_CLASS_BRIDGE_CARDBUS:
  264. pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
  265. status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
  266. pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
  267. break;
  268. }
  269. }
  270. /*
  271. * Now walk the devices again, this time setting them up.
  272. */
  273. list_for_each_entry(dev, &bus->devices, bus_list) {
  274. u16 cmd;
  275. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  276. cmd |= features;
  277. pci_write_config_word(dev, PCI_COMMAND, cmd);
  278. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
  279. L1_CACHE_BYTES >> 2);
  280. }
  281. /*
  282. * Propagate the flags to the PCI bridge.
  283. */
  284. if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
  285. if (features & PCI_COMMAND_FAST_BACK)
  286. bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
  287. if (features & PCI_COMMAND_PARITY)
  288. bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
  289. }
  290. /*
  291. * Report what we did for this bus
  292. */
  293. pr_info("PCI: bus%d: Fast back to back transfers %sabled\n",
  294. bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
  295. }
  296. EXPORT_SYMBOL(pcibios_fixup_bus);
  297. /*
  298. * Swizzle the device pin each time we cross a bridge. If a platform does
  299. * not provide a swizzle function, we perform the standard PCI swizzling.
  300. *
  301. * The default swizzling walks up the bus tree one level at a time, applying
  302. * the standard swizzle function at each step, stopping when it finds the PCI
  303. * root bus. This will return the slot number of the bridge device on the
  304. * root bus and the interrupt pin on that device which should correspond
  305. * with the downstream device interrupt.
  306. *
  307. * Platforms may override this, in which case the slot and pin returned
  308. * depend entirely on the platform code. However, please note that the
  309. * PCI standard swizzle is implemented on plug-in cards and Cardbus based
  310. * PCI extenders, so it can not be ignored.
  311. */
  312. static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin)
  313. {
  314. struct pci_sys_data *sys = dev->sysdata;
  315. int slot, oldpin = *pin;
  316. if (sys->swizzle)
  317. slot = sys->swizzle(dev, pin);
  318. else
  319. slot = pci_common_swizzle(dev, pin);
  320. if (debug_pci)
  321. printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
  322. pci_name(dev), oldpin, *pin, slot);
  323. return slot;
  324. }
  325. /*
  326. * Map a slot/pin to an IRQ.
  327. */
  328. static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  329. {
  330. struct pci_sys_data *sys = dev->sysdata;
  331. int irq = -1;
  332. if (sys->map_irq)
  333. irq = sys->map_irq(dev, slot, pin);
  334. if (debug_pci)
  335. printk("PCI: %s mapping slot %d pin %d => irq %d\n",
  336. pci_name(dev), slot, pin, irq);
  337. return irq;
  338. }
  339. static int pcibios_init_resource(int busnr, struct pci_sys_data *sys)
  340. {
  341. int ret;
  342. struct resource_entry *window;
  343. if (list_empty(&sys->resources)) {
  344. pci_add_resource_offset(&sys->resources,
  345. &iomem_resource, sys->mem_offset);
  346. }
  347. resource_list_for_each_entry(window, &sys->resources)
  348. if (resource_type(window->res) == IORESOURCE_IO)
  349. return 0;
  350. sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io;
  351. sys->io_res.end = (busnr + 1) * SZ_64K - 1;
  352. sys->io_res.flags = IORESOURCE_IO;
  353. sys->io_res.name = sys->io_res_name;
  354. sprintf(sys->io_res_name, "PCI%d I/O", busnr);
  355. ret = request_resource(&ioport_resource, &sys->io_res);
  356. if (ret) {
  357. pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
  358. return ret;
  359. }
  360. pci_add_resource_offset(&sys->resources, &sys->io_res,
  361. sys->io_offset);
  362. return 0;
  363. }
  364. static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
  365. struct list_head *head)
  366. {
  367. struct pci_sys_data *sys = NULL;
  368. int ret;
  369. int nr, busnr;
  370. for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
  371. struct pci_host_bridge *bridge;
  372. bridge = pci_alloc_host_bridge(sizeof(struct pci_sys_data));
  373. if (WARN(!bridge, "PCI: unable to allocate bridge!"))
  374. break;
  375. sys = pci_host_bridge_priv(bridge);
  376. sys->busnr = busnr;
  377. sys->swizzle = hw->swizzle;
  378. sys->map_irq = hw->map_irq;
  379. INIT_LIST_HEAD(&sys->resources);
  380. if (hw->private_data)
  381. sys->private_data = hw->private_data[nr];
  382. ret = hw->setup(nr, sys);
  383. if (ret > 0) {
  384. ret = pcibios_init_resource(nr, sys);
  385. if (ret) {
  386. pci_free_host_bridge(bridge);
  387. break;
  388. }
  389. bridge->map_irq = pcibios_map_irq;
  390. bridge->swizzle_irq = pcibios_swizzle;
  391. if (hw->scan)
  392. ret = hw->scan(nr, bridge);
  393. else {
  394. list_splice_init(&sys->resources,
  395. &bridge->windows);
  396. bridge->dev.parent = parent;
  397. bridge->sysdata = sys;
  398. bridge->busnr = sys->busnr;
  399. bridge->ops = hw->ops;
  400. ret = pci_scan_root_bus_bridge(bridge);
  401. }
  402. if (WARN(ret < 0, "PCI: unable to scan bus!")) {
  403. pci_free_host_bridge(bridge);
  404. break;
  405. }
  406. sys->bus = bridge->bus;
  407. busnr = sys->bus->busn_res.end + 1;
  408. list_add(&sys->node, head);
  409. } else {
  410. pci_free_host_bridge(bridge);
  411. if (ret < 0)
  412. break;
  413. }
  414. }
  415. }
  416. void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
  417. {
  418. struct pci_sys_data *sys;
  419. LIST_HEAD(head);
  420. pci_add_flags(PCI_REASSIGN_ALL_BUS);
  421. if (hw->preinit)
  422. hw->preinit();
  423. pcibios_init_hw(parent, hw, &head);
  424. if (hw->postinit)
  425. hw->postinit();
  426. list_for_each_entry(sys, &head, node) {
  427. struct pci_bus *bus = sys->bus;
  428. /*
  429. * We insert PCI resources into the iomem_resource and
  430. * ioport_resource trees in either pci_bus_claim_resources()
  431. * or pci_bus_assign_resources().
  432. */
  433. if (pci_has_flag(PCI_PROBE_ONLY)) {
  434. pci_bus_claim_resources(bus);
  435. } else {
  436. struct pci_bus *child;
  437. pci_bus_size_bridges(bus);
  438. pci_bus_assign_resources(bus);
  439. list_for_each_entry(child, &bus->children, node)
  440. pcie_bus_configure_settings(child);
  441. }
  442. pci_bus_add_devices(bus);
  443. }
  444. }
  445. #ifndef CONFIG_PCI_HOST_ITE8152
  446. void pcibios_set_master(struct pci_dev *dev)
  447. {
  448. /* No special bus mastering setup handling */
  449. }
  450. #endif
  451. char * __init pcibios_setup(char *str)
  452. {
  453. if (!strcmp(str, "debug")) {
  454. debug_pci = 1;
  455. return NULL;
  456. }
  457. return str;
  458. }
  459. /*
  460. * From arch/i386/kernel/pci-i386.c:
  461. *
  462. * We need to avoid collisions with `mirrored' VGA ports
  463. * and other strange ISA hardware, so we always want the
  464. * addresses to be allocated in the 0x000-0x0ff region
  465. * modulo 0x400.
  466. *
  467. * Why? Because some silly external IO cards only decode
  468. * the low 10 bits of the IO address. The 0x00-0xff region
  469. * is reserved for motherboard devices that decode all 16
  470. * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  471. * but we want to try to avoid allocating at 0x2900-0x2bff
  472. * which might be mirrored at 0x0100-0x03ff..
  473. */
  474. resource_size_t pcibios_align_resource(void *data, const struct resource *res,
  475. resource_size_t size, resource_size_t align)
  476. {
  477. struct pci_dev *dev = data;
  478. resource_size_t start = res->start;
  479. struct pci_host_bridge *host_bridge;
  480. if (res->flags & IORESOURCE_IO && start & 0x300)
  481. start = (start + 0x3ff) & ~0x3ff;
  482. start = (start + align - 1) & ~(align - 1);
  483. host_bridge = pci_find_host_bridge(dev->bus);
  484. if (host_bridge->align_resource)
  485. return host_bridge->align_resource(dev, res,
  486. start, size, align);
  487. return start;
  488. }
  489. void __init pci_map_io_early(unsigned long pfn)
  490. {
  491. struct map_desc pci_io_desc = {
  492. .virtual = PCI_IO_VIRT_BASE,
  493. .type = MT_DEVICE,
  494. .length = SZ_64K,
  495. };
  496. pci_io_desc.pfn = pfn;
  497. iotable_init(&pci_io_desc, 1);
  498. }