zynq.S 1.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Debugging macro include header
  4. *
  5. * Copyright (C) 2011 Xilinx
  6. */
  7. #define UART_CR_OFFSET 0x00 /* Control Register [8:0] */
  8. #define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */
  9. #define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
  10. #define UART_SR_TXFULL 0x00000010 /* TX FIFO full */
  11. #define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
  12. #define UART0_PHYS 0xE0000000
  13. #define UART0_VIRT 0xF0800000
  14. #define UART1_PHYS 0xE0001000
  15. #define UART1_VIRT 0xF0801000
  16. #if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
  17. # define LL_UART_PADDR UART1_PHYS
  18. # define LL_UART_VADDR UART1_VIRT
  19. #else
  20. # define LL_UART_PADDR UART0_PHYS
  21. # define LL_UART_VADDR UART0_VIRT
  22. #endif
  23. .macro addruart, rp, rv, tmp
  24. ldr \rp, =LL_UART_PADDR @ physical
  25. ldr \rv, =LL_UART_VADDR @ virtual
  26. .endm
  27. .macro senduart,rd,rx
  28. strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
  29. .endm
  30. .macro waituartcts,rd,rx
  31. .endm
  32. .macro waituarttxrdy,rd,rx
  33. 1001: ldr \rd, [\rx, #UART_SR_OFFSET]
  34. ARM_BE8( rev \rd, \rd )
  35. tst \rd, #UART_SR_TXEMPTY
  36. beq 1001b
  37. .endm
  38. .macro busyuart,rd,rx
  39. 1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
  40. ARM_BE8( rev \rd, \rd )
  41. tst \rd, #UART_SR_TXFULL @
  42. bne 1002b @ wait if FIFO is full
  43. .endm