v7m.h 3.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Common defines for v7m cpus
  4. */
  5. #define V7M_SCS_ICTR IOMEM(0xe000e004)
  6. #define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
  7. #define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
  8. #define V7M_SCB_CPUID 0x00
  9. #define V7M_SCB_ICSR 0x04
  10. #define V7M_SCB_ICSR_PENDSVSET (1 << 28)
  11. #define V7M_SCB_ICSR_PENDSVCLR (1 << 27)
  12. #define V7M_SCB_ICSR_RETTOBASE (1 << 11)
  13. #define V7M_SCB_ICSR_VECTACTIVE 0x000001ff
  14. #define V7M_SCB_VTOR 0x08
  15. #define V7M_SCB_AIRCR 0x0c
  16. #define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
  17. #define V7M_SCB_AIRCR_SYSRESETREQ (1 << 2)
  18. #define V7M_SCB_SCR 0x10
  19. #define V7M_SCB_SCR_SLEEPDEEP (1 << 2)
  20. #define V7M_SCB_CCR 0x14
  21. #define V7M_SCB_CCR_STKALIGN (1 << 9)
  22. #define V7M_SCB_CCR_DC (1 << 16)
  23. #define V7M_SCB_CCR_IC (1 << 17)
  24. #define V7M_SCB_CCR_BP (1 << 18)
  25. #define V7M_SCB_SHPR2 0x1c
  26. #define V7M_SCB_SHPR3 0x20
  27. #define V7M_SCB_SHCSR 0x24
  28. #define V7M_SCB_SHCSR_USGFAULTENA (1 << 18)
  29. #define V7M_SCB_SHCSR_BUSFAULTENA (1 << 17)
  30. #define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16)
  31. #define V7M_xPSR_FRAMEPTRALIGN 0x00000200
  32. #define V7M_xPSR_EXCEPTIONNO V7M_SCB_ICSR_VECTACTIVE
  33. /*
  34. * When branching to an address that has bits [31:28] == 0xf an exception return
  35. * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP
  36. * extension Bit [4] defines if the exception frame has space allocated for FP
  37. * state information, SBOP otherwise. Bit [3] defines the mode that is returned
  38. * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
  39. * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
  40. */
  41. #define EXC_RET_STACK_MASK 0x00000004
  42. #define EXC_RET_THREADMODE_PROCESSSTACK (3 << 2)
  43. /* Cache related definitions */
  44. #define V7M_SCB_CLIDR 0x78 /* Cache Level ID register */
  45. #define V7M_SCB_CTR 0x7c /* Cache Type register */
  46. #define V7M_SCB_CCSIDR 0x80 /* Cache size ID register */
  47. #define V7M_SCB_CSSELR 0x84 /* Cache size selection register */
  48. /* Memory-mapped MPU registers for M-class */
  49. #define MPU_TYPE 0x90
  50. #define MPU_CTRL 0x94
  51. #define MPU_CTRL_ENABLE 1
  52. #define MPU_CTRL_PRIVDEFENA (1 << 2)
  53. #define PMSAv7_RNR 0x98
  54. #define PMSAv7_RBAR 0x9c
  55. #define PMSAv7_RASR 0xa0
  56. #define PMSAv8_RNR 0x98
  57. #define PMSAv8_RBAR 0x9c
  58. #define PMSAv8_RLAR 0xa0
  59. #define PMSAv8_RBAR_A(n) (PMSAv8_RBAR + 8*(n))
  60. #define PMSAv8_RLAR_A(n) (PMSAv8_RLAR + 8*(n))
  61. #define PMSAv8_MAIR0 0xc0
  62. #define PMSAv8_MAIR1 0xc4
  63. /* Cache opeartions */
  64. #define V7M_SCB_ICIALLU 0x250 /* I-cache invalidate all to PoU */
  65. #define V7M_SCB_ICIMVAU 0x258 /* I-cache invalidate by MVA to PoU */
  66. #define V7M_SCB_DCIMVAC 0x25c /* D-cache invalidate by MVA to PoC */
  67. #define V7M_SCB_DCISW 0x260 /* D-cache invalidate by set-way */
  68. #define V7M_SCB_DCCMVAU 0x264 /* D-cache clean by MVA to PoU */
  69. #define V7M_SCB_DCCMVAC 0x268 /* D-cache clean by MVA to PoC */
  70. #define V7M_SCB_DCCSW 0x26c /* D-cache clean by set-way */
  71. #define V7M_SCB_DCCIMVAC 0x270 /* D-cache clean and invalidate by MVA to PoC */
  72. #define V7M_SCB_DCCISW 0x274 /* D-cache clean and invalidate by set-way */
  73. #define V7M_SCB_BPIALL 0x278 /* D-cache clean and invalidate by set-way */
  74. #ifndef __ASSEMBLY__
  75. enum reboot_mode;
  76. void armv7m_restart(enum reboot_mode mode, const char *cmd);
  77. #endif /* __ASSEMBLY__ */