tls.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef __ASMARM_TLS_H
  3. #define __ASMARM_TLS_H
  4. #include <linux/compiler.h>
  5. #include <asm/thread_info.h>
  6. #ifdef __ASSEMBLY__
  7. #include <asm/asm-offsets.h>
  8. .macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
  9. .endm
  10. .macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2
  11. mrc p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
  12. @ TLS register update is deferred until return to user space
  13. mcr p15, 0, \tpuser, c13, c0, 2 @ set the user r/w register
  14. str \tmp2, [\base, #TI_TP_VALUE + 4] @ save it
  15. .endm
  16. .macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2
  17. #ifdef CONFIG_SMP
  18. ALT_SMP(nop)
  19. ALT_UP_B(.L0_\@)
  20. .subsection 1
  21. #endif
  22. .L0_\@:
  23. ldr_va \tmp1, elf_hwcap
  24. mov \tmp2, #0xffff0fff
  25. tst \tmp1, #HWCAP_TLS @ hardware TLS available?
  26. streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0
  27. beq .L2_\@
  28. mcr p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
  29. #ifdef CONFIG_SMP
  30. b .L1_\@
  31. .previous
  32. #endif
  33. .L1_\@: switch_tls_v6k \base, \tp, \tpuser, \tmp1, \tmp2
  34. .L2_\@:
  35. .endm
  36. .macro switch_tls_software, base, tp, tpuser, tmp1, tmp2
  37. mov \tmp1, #0xffff0fff
  38. str \tp, [\tmp1, #-15] @ set TLS value at 0xffff0ff0
  39. .endm
  40. #else
  41. #include <asm/smp_plat.h>
  42. #endif
  43. #ifdef CONFIG_TLS_REG_EMUL
  44. #define tls_emu 1
  45. #define has_tls_reg 1
  46. #define defer_tls_reg_update 0
  47. #define switch_tls switch_tls_none
  48. #elif defined(CONFIG_CPU_V6)
  49. #define tls_emu 0
  50. #define has_tls_reg (elf_hwcap & HWCAP_TLS)
  51. #define defer_tls_reg_update is_smp()
  52. #define switch_tls switch_tls_v6
  53. #elif defined(CONFIG_CPU_32v6K)
  54. #define tls_emu 0
  55. #define has_tls_reg 1
  56. #define defer_tls_reg_update 1
  57. #define switch_tls switch_tls_v6k
  58. #else
  59. #define tls_emu 0
  60. #define has_tls_reg 0
  61. #define defer_tls_reg_update 0
  62. #define switch_tls switch_tls_software
  63. #endif
  64. #ifndef __ASSEMBLY__
  65. static inline void set_tls(unsigned long val)
  66. {
  67. struct thread_info *thread;
  68. thread = current_thread_info();
  69. thread->tp_value[0] = val;
  70. /*
  71. * This code runs with preemption enabled and therefore must
  72. * be reentrant with respect to switch_tls.
  73. *
  74. * We need to ensure ordering between the shadow state and the
  75. * hardware state, so that we don't corrupt the hardware state
  76. * with a stale shadow state during context switch.
  77. *
  78. * If we're preempted here, switch_tls will load TPIDRURO from
  79. * thread_info upon resuming execution and the following mcr
  80. * is merely redundant.
  81. */
  82. barrier();
  83. if (!tls_emu) {
  84. if (has_tls_reg && !defer_tls_reg_update) {
  85. asm("mcr p15, 0, %0, c13, c0, 3"
  86. : : "r" (val));
  87. } else if (!has_tls_reg) {
  88. #ifdef CONFIG_KUSER_HELPERS
  89. /*
  90. * User space must never try to access this
  91. * directly. Expect your app to break
  92. * eventually if you do so. The user helper
  93. * at 0xffff0fe0 must be used instead. (see
  94. * entry-armv.S for details)
  95. */
  96. *((unsigned int *)0xffff0ff0) = val;
  97. #endif
  98. }
  99. }
  100. }
  101. static inline unsigned long get_tpuser(void)
  102. {
  103. unsigned long reg = 0;
  104. if (has_tls_reg && !tls_emu)
  105. __asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (reg));
  106. return reg;
  107. }
  108. static inline void set_tpuser(unsigned long val)
  109. {
  110. /* Since TPIDRURW is fully context-switched (unlike TPIDRURO),
  111. * we need not update thread_info.
  112. */
  113. if (has_tls_reg && !tls_emu) {
  114. asm("mcr p15, 0, %0, c13, c0, 2"
  115. : : "r" (val));
  116. }
  117. }
  118. static inline void flush_tls(void)
  119. {
  120. set_tls(0);
  121. set_tpuser(0);
  122. }
  123. #endif
  124. #endif /* __ASMARM_TLS_H */