ioc.h 1.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * arch/arm/include/asm/hardware/ioc.h
  4. *
  5. * Copyright (C) Russell King
  6. *
  7. * Use these macros to read/write the IOC. All it does is perform the actual
  8. * read/write.
  9. */
  10. #ifndef __ASMARM_HARDWARE_IOC_H
  11. #define __ASMARM_HARDWARE_IOC_H
  12. #ifndef __ASSEMBLY__
  13. /*
  14. * We use __raw_base variants here so that we give the compiler the
  15. * chance to keep IOC_BASE in a register.
  16. */
  17. #define ioc_readb(off) __raw_readb(IOC_BASE + (off))
  18. #define ioc_writeb(val,off) __raw_writeb(val, IOC_BASE + (off))
  19. #endif
  20. #define IOC_CONTROL (0x00)
  21. #define IOC_KARTTX (0x04)
  22. #define IOC_KARTRX (0x04)
  23. #define IOC_IRQSTATA (0x10)
  24. #define IOC_IRQREQA (0x14)
  25. #define IOC_IRQCLRA (0x14)
  26. #define IOC_IRQMASKA (0x18)
  27. #define IOC_IRQSTATB (0x20)
  28. #define IOC_IRQREQB (0x24)
  29. #define IOC_IRQMASKB (0x28)
  30. #define IOC_FIQSTAT (0x30)
  31. #define IOC_FIQREQ (0x34)
  32. #define IOC_FIQMASK (0x38)
  33. #define IOC_T0CNTL (0x40)
  34. #define IOC_T0LTCHL (0x40)
  35. #define IOC_T0CNTH (0x44)
  36. #define IOC_T0LTCHH (0x44)
  37. #define IOC_T0GO (0x48)
  38. #define IOC_T0LATCH (0x4c)
  39. #define IOC_T1CNTL (0x50)
  40. #define IOC_T1LTCHL (0x50)
  41. #define IOC_T1CNTH (0x54)
  42. #define IOC_T1LTCHH (0x54)
  43. #define IOC_T1GO (0x58)
  44. #define IOC_T1LATCH (0x5c)
  45. #define IOC_T2CNTL (0x60)
  46. #define IOC_T2LTCHL (0x60)
  47. #define IOC_T2CNTH (0x64)
  48. #define IOC_T2LTCHH (0x64)
  49. #define IOC_T2GO (0x68)
  50. #define IOC_T2LATCH (0x6c)
  51. #define IOC_T3CNTL (0x70)
  52. #define IOC_T3LTCHL (0x70)
  53. #define IOC_T3CNTH (0x74)
  54. #define IOC_T3LTCHH (0x74)
  55. #define IOC_T3GO (0x78)
  56. #define IOC_T3LATCH (0x7c)
  57. #endif