sa1111.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/common/sa1111.c
  4. *
  5. * SA1111 support
  6. *
  7. * Original code by John Dorsey
  8. *
  9. * This file contains all generic SA1111 support.
  10. *
  11. * All initialization functions provided here are intended to be called
  12. * from machine specific code with proper arguments when required.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/gpio/driver.h>
  16. #include <linux/init.h>
  17. #include <linux/irq.h>
  18. #include <linux/kernel.h>
  19. #include <linux/delay.h>
  20. #include <linux/errno.h>
  21. #include <linux/ioport.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/slab.h>
  24. #include <linux/spinlock.h>
  25. #include <linux/dma-map-ops.h>
  26. #include <linux/clk.h>
  27. #include <linux/io.h>
  28. #include <asm/mach/irq.h>
  29. #include <asm/mach-types.h>
  30. #include <linux/sizes.h>
  31. #include <asm/hardware/sa1111.h>
  32. #ifdef CONFIG_ARCH_SA1100
  33. #include <mach/hardware.h>
  34. #endif
  35. /* SA1111 IRQs */
  36. #define IRQ_GPAIN0 (0)
  37. #define IRQ_GPAIN1 (1)
  38. #define IRQ_GPAIN2 (2)
  39. #define IRQ_GPAIN3 (3)
  40. #define IRQ_GPBIN0 (4)
  41. #define IRQ_GPBIN1 (5)
  42. #define IRQ_GPBIN2 (6)
  43. #define IRQ_GPBIN3 (7)
  44. #define IRQ_GPBIN4 (8)
  45. #define IRQ_GPBIN5 (9)
  46. #define IRQ_GPCIN0 (10)
  47. #define IRQ_GPCIN1 (11)
  48. #define IRQ_GPCIN2 (12)
  49. #define IRQ_GPCIN3 (13)
  50. #define IRQ_GPCIN4 (14)
  51. #define IRQ_GPCIN5 (15)
  52. #define IRQ_GPCIN6 (16)
  53. #define IRQ_GPCIN7 (17)
  54. #define IRQ_MSTXINT (18)
  55. #define IRQ_MSRXINT (19)
  56. #define IRQ_MSSTOPERRINT (20)
  57. #define IRQ_TPTXINT (21)
  58. #define IRQ_TPRXINT (22)
  59. #define IRQ_TPSTOPERRINT (23)
  60. #define SSPXMTINT (24)
  61. #define SSPRCVINT (25)
  62. #define SSPROR (26)
  63. #define AUDXMTDMADONEA (32)
  64. #define AUDRCVDMADONEA (33)
  65. #define AUDXMTDMADONEB (34)
  66. #define AUDRCVDMADONEB (35)
  67. #define AUDTFSR (36)
  68. #define AUDRFSR (37)
  69. #define AUDTUR (38)
  70. #define AUDROR (39)
  71. #define AUDDTS (40)
  72. #define AUDRDD (41)
  73. #define AUDSTO (42)
  74. #define IRQ_USBPWR (43)
  75. #define IRQ_HCIM (44)
  76. #define IRQ_HCIBUFFACC (45)
  77. #define IRQ_HCIRMTWKP (46)
  78. #define IRQ_NHCIMFCIR (47)
  79. #define IRQ_USB_PORT_RESUME (48)
  80. #define IRQ_S0_READY_NINT (49)
  81. #define IRQ_S1_READY_NINT (50)
  82. #define IRQ_S0_CD_VALID (51)
  83. #define IRQ_S1_CD_VALID (52)
  84. #define IRQ_S0_BVD1_STSCHG (53)
  85. #define IRQ_S1_BVD1_STSCHG (54)
  86. #define SA1111_IRQ_NR (55)
  87. extern void sa1110_mb_enable(void);
  88. extern void sa1110_mb_disable(void);
  89. /*
  90. * We keep the following data for the overall SA1111. Note that the
  91. * struct device and struct resource are "fake"; they should be supplied
  92. * by the bus above us. However, in the interests of getting all SA1111
  93. * drivers converted over to the device model, we provide this as an
  94. * anchor point for all the other drivers.
  95. */
  96. struct sa1111 {
  97. struct device *dev;
  98. struct clk *clk;
  99. unsigned long phys;
  100. int irq;
  101. int irq_base; /* base for cascaded on-chip IRQs */
  102. spinlock_t lock;
  103. void __iomem *base;
  104. struct sa1111_platform_data *pdata;
  105. struct irq_domain *irqdomain;
  106. struct gpio_chip gc;
  107. #ifdef CONFIG_PM
  108. void *saved_state;
  109. #endif
  110. };
  111. /*
  112. * We _really_ need to eliminate this. Its only users
  113. * are the PWM and DMA checking code.
  114. */
  115. static struct sa1111 *g_sa1111;
  116. struct sa1111_dev_info {
  117. unsigned long offset;
  118. unsigned long skpcr_mask;
  119. bool dma;
  120. unsigned int devid;
  121. unsigned int hwirq[6];
  122. };
  123. static struct sa1111_dev_info sa1111_devices[] = {
  124. {
  125. .offset = SA1111_USB,
  126. .skpcr_mask = SKPCR_UCLKEN,
  127. .dma = true,
  128. .devid = SA1111_DEVID_USB,
  129. .hwirq = {
  130. IRQ_USBPWR,
  131. IRQ_HCIM,
  132. IRQ_HCIBUFFACC,
  133. IRQ_HCIRMTWKP,
  134. IRQ_NHCIMFCIR,
  135. IRQ_USB_PORT_RESUME
  136. },
  137. },
  138. {
  139. .offset = 0x0600,
  140. .skpcr_mask = SKPCR_I2SCLKEN | SKPCR_L3CLKEN,
  141. .dma = true,
  142. .devid = SA1111_DEVID_SAC,
  143. .hwirq = {
  144. AUDXMTDMADONEA,
  145. AUDXMTDMADONEB,
  146. AUDRCVDMADONEA,
  147. AUDRCVDMADONEB
  148. },
  149. },
  150. {
  151. .offset = 0x0800,
  152. .skpcr_mask = SKPCR_SCLKEN,
  153. .devid = SA1111_DEVID_SSP,
  154. },
  155. {
  156. .offset = SA1111_KBD,
  157. .skpcr_mask = SKPCR_PTCLKEN,
  158. .devid = SA1111_DEVID_PS2_KBD,
  159. .hwirq = {
  160. IRQ_TPRXINT,
  161. IRQ_TPTXINT
  162. },
  163. },
  164. {
  165. .offset = SA1111_MSE,
  166. .skpcr_mask = SKPCR_PMCLKEN,
  167. .devid = SA1111_DEVID_PS2_MSE,
  168. .hwirq = {
  169. IRQ_MSRXINT,
  170. IRQ_MSTXINT
  171. },
  172. },
  173. {
  174. .offset = 0x1800,
  175. .skpcr_mask = 0,
  176. .devid = SA1111_DEVID_PCMCIA,
  177. .hwirq = {
  178. IRQ_S0_READY_NINT,
  179. IRQ_S0_CD_VALID,
  180. IRQ_S0_BVD1_STSCHG,
  181. IRQ_S1_READY_NINT,
  182. IRQ_S1_CD_VALID,
  183. IRQ_S1_BVD1_STSCHG,
  184. },
  185. },
  186. };
  187. static int sa1111_map_irq(struct sa1111 *sachip, irq_hw_number_t hwirq)
  188. {
  189. return irq_create_mapping(sachip->irqdomain, hwirq);
  190. }
  191. /*
  192. * SA1111 interrupt support. Since clearing an IRQ while there are
  193. * active IRQs causes the interrupt output to pulse, the upper levels
  194. * will call us again if there are more interrupts to process.
  195. */
  196. static void sa1111_irq_handler(struct irq_desc *desc)
  197. {
  198. unsigned int stat0, stat1, i;
  199. struct sa1111 *sachip = irq_desc_get_handler_data(desc);
  200. struct irq_domain *irqdomain;
  201. void __iomem *mapbase = sachip->base + SA1111_INTC;
  202. stat0 = readl_relaxed(mapbase + SA1111_INTSTATCLR0);
  203. stat1 = readl_relaxed(mapbase + SA1111_INTSTATCLR1);
  204. writel_relaxed(stat0, mapbase + SA1111_INTSTATCLR0);
  205. desc->irq_data.chip->irq_ack(&desc->irq_data);
  206. writel_relaxed(stat1, mapbase + SA1111_INTSTATCLR1);
  207. if (stat0 == 0 && stat1 == 0) {
  208. do_bad_IRQ(desc);
  209. return;
  210. }
  211. irqdomain = sachip->irqdomain;
  212. for (i = 0; stat0; i++, stat0 >>= 1)
  213. if (stat0 & 1)
  214. generic_handle_domain_irq(irqdomain, i);
  215. for (i = 32; stat1; i++, stat1 >>= 1)
  216. if (stat1 & 1)
  217. generic_handle_domain_irq(irqdomain, i);
  218. /* For level-based interrupts */
  219. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  220. }
  221. static u32 sa1111_irqmask(struct irq_data *d)
  222. {
  223. return BIT(irqd_to_hwirq(d) & 31);
  224. }
  225. static int sa1111_irqbank(struct irq_data *d)
  226. {
  227. return (irqd_to_hwirq(d) / 32) * 4;
  228. }
  229. static void sa1111_ack_irq(struct irq_data *d)
  230. {
  231. }
  232. static void sa1111_mask_irq(struct irq_data *d)
  233. {
  234. struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
  235. void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
  236. u32 ie;
  237. ie = readl_relaxed(mapbase + SA1111_INTEN0);
  238. ie &= ~sa1111_irqmask(d);
  239. writel(ie, mapbase + SA1111_INTEN0);
  240. }
  241. static void sa1111_unmask_irq(struct irq_data *d)
  242. {
  243. struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
  244. void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
  245. u32 ie;
  246. ie = readl_relaxed(mapbase + SA1111_INTEN0);
  247. ie |= sa1111_irqmask(d);
  248. writel_relaxed(ie, mapbase + SA1111_INTEN0);
  249. }
  250. /*
  251. * Attempt to re-trigger the interrupt. The SA1111 contains a register
  252. * (INTSET) which claims to do this. However, in practice no amount of
  253. * manipulation of INTEN and INTSET guarantees that the interrupt will
  254. * be triggered. In fact, its very difficult, if not impossible to get
  255. * INTSET to re-trigger the interrupt.
  256. */
  257. static int sa1111_retrigger_irq(struct irq_data *d)
  258. {
  259. struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
  260. void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
  261. u32 ip, mask = sa1111_irqmask(d);
  262. int i;
  263. ip = readl_relaxed(mapbase + SA1111_INTPOL0);
  264. for (i = 0; i < 8; i++) {
  265. writel_relaxed(ip ^ mask, mapbase + SA1111_INTPOL0);
  266. writel_relaxed(ip, mapbase + SA1111_INTPOL0);
  267. if (readl_relaxed(mapbase + SA1111_INTSTATCLR0) & mask)
  268. break;
  269. }
  270. if (i == 8) {
  271. pr_err("Danger Will Robinson: failed to re-trigger IRQ%d\n",
  272. d->irq);
  273. return 0;
  274. }
  275. return 1;
  276. }
  277. static int sa1111_type_irq(struct irq_data *d, unsigned int flags)
  278. {
  279. struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
  280. void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
  281. u32 ip, mask = sa1111_irqmask(d);
  282. if (flags == IRQ_TYPE_PROBE)
  283. return 0;
  284. if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0)
  285. return -EINVAL;
  286. ip = readl_relaxed(mapbase + SA1111_INTPOL0);
  287. if (flags & IRQ_TYPE_EDGE_RISING)
  288. ip &= ~mask;
  289. else
  290. ip |= mask;
  291. writel_relaxed(ip, mapbase + SA1111_INTPOL0);
  292. writel_relaxed(ip, mapbase + SA1111_WAKEPOL0);
  293. return 0;
  294. }
  295. static int sa1111_wake_irq(struct irq_data *d, unsigned int on)
  296. {
  297. struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
  298. void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
  299. u32 we, mask = sa1111_irqmask(d);
  300. we = readl_relaxed(mapbase + SA1111_WAKEEN0);
  301. if (on)
  302. we |= mask;
  303. else
  304. we &= ~mask;
  305. writel_relaxed(we, mapbase + SA1111_WAKEEN0);
  306. return 0;
  307. }
  308. static struct irq_chip sa1111_irq_chip = {
  309. .name = "SA1111",
  310. .irq_ack = sa1111_ack_irq,
  311. .irq_mask = sa1111_mask_irq,
  312. .irq_unmask = sa1111_unmask_irq,
  313. .irq_retrigger = sa1111_retrigger_irq,
  314. .irq_set_type = sa1111_type_irq,
  315. .irq_set_wake = sa1111_wake_irq,
  316. };
  317. static int sa1111_irqdomain_map(struct irq_domain *d, unsigned int irq,
  318. irq_hw_number_t hwirq)
  319. {
  320. struct sa1111 *sachip = d->host_data;
  321. /* Disallow unavailable interrupts */
  322. if (hwirq > SSPROR && hwirq < AUDXMTDMADONEA)
  323. return -EINVAL;
  324. irq_set_chip_data(irq, sachip);
  325. irq_set_chip_and_handler(irq, &sa1111_irq_chip, handle_edge_irq);
  326. irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
  327. return 0;
  328. }
  329. static const struct irq_domain_ops sa1111_irqdomain_ops = {
  330. .map = sa1111_irqdomain_map,
  331. .xlate = irq_domain_xlate_twocell,
  332. };
  333. static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base)
  334. {
  335. void __iomem *irqbase = sachip->base + SA1111_INTC;
  336. int ret;
  337. /*
  338. * We're guaranteed that this region hasn't been taken.
  339. */
  340. request_mem_region(sachip->phys + SA1111_INTC, 512, "irq");
  341. ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1);
  342. if (ret <= 0) {
  343. dev_err(sachip->dev, "unable to allocate %u irqs: %d\n",
  344. SA1111_IRQ_NR, ret);
  345. if (ret == 0)
  346. ret = -EINVAL;
  347. return ret;
  348. }
  349. sachip->irq_base = ret;
  350. /* disable all IRQs */
  351. writel_relaxed(0, irqbase + SA1111_INTEN0);
  352. writel_relaxed(0, irqbase + SA1111_INTEN1);
  353. writel_relaxed(0, irqbase + SA1111_WAKEEN0);
  354. writel_relaxed(0, irqbase + SA1111_WAKEEN1);
  355. /*
  356. * detect on rising edge. Note: Feb 2001 Errata for SA1111
  357. * specifies that S0ReadyInt and S1ReadyInt should be '1'.
  358. */
  359. writel_relaxed(0, irqbase + SA1111_INTPOL0);
  360. writel_relaxed(BIT(IRQ_S0_READY_NINT & 31) |
  361. BIT(IRQ_S1_READY_NINT & 31),
  362. irqbase + SA1111_INTPOL1);
  363. /* clear all IRQs */
  364. writel_relaxed(~0, irqbase + SA1111_INTSTATCLR0);
  365. writel_relaxed(~0, irqbase + SA1111_INTSTATCLR1);
  366. sachip->irqdomain = irq_domain_add_linear(NULL, SA1111_IRQ_NR,
  367. &sa1111_irqdomain_ops,
  368. sachip);
  369. if (!sachip->irqdomain) {
  370. irq_free_descs(sachip->irq_base, SA1111_IRQ_NR);
  371. return -ENOMEM;
  372. }
  373. irq_domain_associate_many(sachip->irqdomain,
  374. sachip->irq_base + IRQ_GPAIN0,
  375. IRQ_GPAIN0, SSPROR + 1 - IRQ_GPAIN0);
  376. irq_domain_associate_many(sachip->irqdomain,
  377. sachip->irq_base + AUDXMTDMADONEA,
  378. AUDXMTDMADONEA,
  379. IRQ_S1_BVD1_STSCHG + 1 - AUDXMTDMADONEA);
  380. /*
  381. * Register SA1111 interrupt
  382. */
  383. irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
  384. irq_set_chained_handler_and_data(sachip->irq, sa1111_irq_handler,
  385. sachip);
  386. dev_info(sachip->dev, "Providing IRQ%u-%u\n",
  387. sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1);
  388. return 0;
  389. }
  390. static void sa1111_remove_irq(struct sa1111 *sachip)
  391. {
  392. struct irq_domain *domain = sachip->irqdomain;
  393. void __iomem *irqbase = sachip->base + SA1111_INTC;
  394. int i;
  395. /* disable all IRQs */
  396. writel_relaxed(0, irqbase + SA1111_INTEN0);
  397. writel_relaxed(0, irqbase + SA1111_INTEN1);
  398. writel_relaxed(0, irqbase + SA1111_WAKEEN0);
  399. writel_relaxed(0, irqbase + SA1111_WAKEEN1);
  400. irq_set_chained_handler_and_data(sachip->irq, NULL, NULL);
  401. for (i = 0; i < SA1111_IRQ_NR; i++)
  402. irq_dispose_mapping(irq_find_mapping(domain, i));
  403. irq_domain_remove(domain);
  404. release_mem_region(sachip->phys + SA1111_INTC, 512);
  405. }
  406. enum {
  407. SA1111_GPIO_PXDDR = (SA1111_GPIO_PADDR - SA1111_GPIO_PADDR),
  408. SA1111_GPIO_PXDRR = (SA1111_GPIO_PADRR - SA1111_GPIO_PADDR),
  409. SA1111_GPIO_PXDWR = (SA1111_GPIO_PADWR - SA1111_GPIO_PADDR),
  410. SA1111_GPIO_PXSDR = (SA1111_GPIO_PASDR - SA1111_GPIO_PADDR),
  411. SA1111_GPIO_PXSSR = (SA1111_GPIO_PASSR - SA1111_GPIO_PADDR),
  412. };
  413. static struct sa1111 *gc_to_sa1111(struct gpio_chip *gc)
  414. {
  415. return container_of(gc, struct sa1111, gc);
  416. }
  417. static void __iomem *sa1111_gpio_map_reg(struct sa1111 *sachip, unsigned offset)
  418. {
  419. void __iomem *reg = sachip->base + SA1111_GPIO;
  420. if (offset < 4)
  421. return reg + SA1111_GPIO_PADDR;
  422. if (offset < 10)
  423. return reg + SA1111_GPIO_PBDDR;
  424. if (offset < 18)
  425. return reg + SA1111_GPIO_PCDDR;
  426. return NULL;
  427. }
  428. static u32 sa1111_gpio_map_bit(unsigned offset)
  429. {
  430. if (offset < 4)
  431. return BIT(offset);
  432. if (offset < 10)
  433. return BIT(offset - 4);
  434. if (offset < 18)
  435. return BIT(offset - 10);
  436. return 0;
  437. }
  438. static void sa1111_gpio_modify(void __iomem *reg, u32 mask, u32 set)
  439. {
  440. u32 val;
  441. val = readl_relaxed(reg);
  442. val &= ~mask;
  443. val |= mask & set;
  444. writel_relaxed(val, reg);
  445. }
  446. static int sa1111_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
  447. {
  448. struct sa1111 *sachip = gc_to_sa1111(gc);
  449. void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
  450. u32 mask = sa1111_gpio_map_bit(offset);
  451. return !!(readl_relaxed(reg + SA1111_GPIO_PXDDR) & mask);
  452. }
  453. static int sa1111_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
  454. {
  455. struct sa1111 *sachip = gc_to_sa1111(gc);
  456. unsigned long flags;
  457. void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
  458. u32 mask = sa1111_gpio_map_bit(offset);
  459. spin_lock_irqsave(&sachip->lock, flags);
  460. sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, mask);
  461. sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, mask);
  462. spin_unlock_irqrestore(&sachip->lock, flags);
  463. return 0;
  464. }
  465. static int sa1111_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
  466. int value)
  467. {
  468. struct sa1111 *sachip = gc_to_sa1111(gc);
  469. unsigned long flags;
  470. void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
  471. u32 mask = sa1111_gpio_map_bit(offset);
  472. spin_lock_irqsave(&sachip->lock, flags);
  473. sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0);
  474. sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0);
  475. sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, 0);
  476. sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, 0);
  477. spin_unlock_irqrestore(&sachip->lock, flags);
  478. return 0;
  479. }
  480. static int sa1111_gpio_get(struct gpio_chip *gc, unsigned offset)
  481. {
  482. struct sa1111 *sachip = gc_to_sa1111(gc);
  483. void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
  484. u32 mask = sa1111_gpio_map_bit(offset);
  485. return !!(readl_relaxed(reg + SA1111_GPIO_PXDRR) & mask);
  486. }
  487. static void sa1111_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
  488. {
  489. struct sa1111 *sachip = gc_to_sa1111(gc);
  490. unsigned long flags;
  491. void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
  492. u32 mask = sa1111_gpio_map_bit(offset);
  493. spin_lock_irqsave(&sachip->lock, flags);
  494. sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0);
  495. sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0);
  496. spin_unlock_irqrestore(&sachip->lock, flags);
  497. }
  498. static void sa1111_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
  499. unsigned long *bits)
  500. {
  501. struct sa1111 *sachip = gc_to_sa1111(gc);
  502. unsigned long flags;
  503. void __iomem *reg = sachip->base + SA1111_GPIO;
  504. u32 msk, val;
  505. msk = *mask;
  506. val = *bits;
  507. spin_lock_irqsave(&sachip->lock, flags);
  508. sa1111_gpio_modify(reg + SA1111_GPIO_PADWR, msk & 15, val);
  509. sa1111_gpio_modify(reg + SA1111_GPIO_PASSR, msk & 15, val);
  510. sa1111_gpio_modify(reg + SA1111_GPIO_PBDWR, (msk >> 4) & 255, val >> 4);
  511. sa1111_gpio_modify(reg + SA1111_GPIO_PBSSR, (msk >> 4) & 255, val >> 4);
  512. sa1111_gpio_modify(reg + SA1111_GPIO_PCDWR, (msk >> 12) & 255, val >> 12);
  513. sa1111_gpio_modify(reg + SA1111_GPIO_PCSSR, (msk >> 12) & 255, val >> 12);
  514. spin_unlock_irqrestore(&sachip->lock, flags);
  515. }
  516. static int sa1111_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
  517. {
  518. struct sa1111 *sachip = gc_to_sa1111(gc);
  519. return sa1111_map_irq(sachip, offset);
  520. }
  521. static int sa1111_setup_gpios(struct sa1111 *sachip)
  522. {
  523. sachip->gc.label = "sa1111";
  524. sachip->gc.parent = sachip->dev;
  525. sachip->gc.owner = THIS_MODULE;
  526. sachip->gc.get_direction = sa1111_gpio_get_direction;
  527. sachip->gc.direction_input = sa1111_gpio_direction_input;
  528. sachip->gc.direction_output = sa1111_gpio_direction_output;
  529. sachip->gc.get = sa1111_gpio_get;
  530. sachip->gc.set = sa1111_gpio_set;
  531. sachip->gc.set_multiple = sa1111_gpio_set_multiple;
  532. sachip->gc.to_irq = sa1111_gpio_to_irq;
  533. sachip->gc.base = -1;
  534. sachip->gc.ngpio = 18;
  535. return devm_gpiochip_add_data(sachip->dev, &sachip->gc, sachip);
  536. }
  537. /*
  538. * Bring the SA1111 out of reset. This requires a set procedure:
  539. * 1. nRESET asserted (by hardware)
  540. * 2. CLK turned on from SA1110
  541. * 3. nRESET deasserted
  542. * 4. VCO turned on, PLL_BYPASS turned off
  543. * 5. Wait lock time, then assert RCLKEn
  544. * 7. PCR set to allow clocking of individual functions
  545. *
  546. * Until we've done this, the only registers we can access are:
  547. * SBI_SKCR
  548. * SBI_SMCR
  549. * SBI_SKID
  550. */
  551. static void sa1111_wake(struct sa1111 *sachip)
  552. {
  553. unsigned long flags, r;
  554. spin_lock_irqsave(&sachip->lock, flags);
  555. clk_enable(sachip->clk);
  556. /*
  557. * Turn VCO on, and disable PLL Bypass.
  558. */
  559. r = readl_relaxed(sachip->base + SA1111_SKCR);
  560. r &= ~SKCR_VCO_OFF;
  561. writel_relaxed(r, sachip->base + SA1111_SKCR);
  562. r |= SKCR_PLL_BYPASS | SKCR_OE_EN;
  563. writel_relaxed(r, sachip->base + SA1111_SKCR);
  564. /*
  565. * Wait lock time. SA1111 manual _doesn't_
  566. * specify a figure for this! We choose 100us.
  567. */
  568. udelay(100);
  569. /*
  570. * Enable RCLK. We also ensure that RDYEN is set.
  571. */
  572. r |= SKCR_RCLKEN | SKCR_RDYEN;
  573. writel_relaxed(r, sachip->base + SA1111_SKCR);
  574. /*
  575. * Wait 14 RCLK cycles for the chip to finish coming out
  576. * of reset. (RCLK=24MHz). This is 590ns.
  577. */
  578. udelay(1);
  579. /*
  580. * Ensure all clocks are initially off.
  581. */
  582. writel_relaxed(0, sachip->base + SA1111_SKPCR);
  583. spin_unlock_irqrestore(&sachip->lock, flags);
  584. }
  585. #ifdef CONFIG_ARCH_SA1100
  586. static u32 sa1111_dma_mask[] = {
  587. ~0,
  588. ~(1 << 20),
  589. ~(1 << 23),
  590. ~(1 << 24),
  591. ~(1 << 25),
  592. ~(1 << 20),
  593. ~(1 << 20),
  594. 0,
  595. };
  596. /*
  597. * Configure the SA1111 shared memory controller.
  598. */
  599. void
  600. sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac,
  601. unsigned int cas_latency)
  602. {
  603. unsigned int smcr = SMCR_DTIM | SMCR_MBGE | FInsrt(drac, SMCR_DRAC);
  604. if (cas_latency == 3)
  605. smcr |= SMCR_CLAT;
  606. writel_relaxed(smcr, sachip->base + SA1111_SMCR);
  607. /*
  608. * Now clear the bits in the DMA mask to work around the SA1111
  609. * DMA erratum (Intel StrongARM SA-1111 Microprocessor Companion
  610. * Chip Specification Update, June 2000, Erratum #7).
  611. */
  612. if (sachip->dev->dma_mask)
  613. *sachip->dev->dma_mask &= sa1111_dma_mask[drac >> 2];
  614. sachip->dev->coherent_dma_mask &= sa1111_dma_mask[drac >> 2];
  615. }
  616. #endif
  617. static void sa1111_dev_release(struct device *_dev)
  618. {
  619. struct sa1111_dev *dev = to_sa1111_device(_dev);
  620. kfree(dev);
  621. }
  622. static int
  623. sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent,
  624. struct sa1111_dev_info *info)
  625. {
  626. struct sa1111_dev *dev;
  627. unsigned i;
  628. int ret;
  629. dev = kzalloc(sizeof(struct sa1111_dev), GFP_KERNEL);
  630. if (!dev) {
  631. ret = -ENOMEM;
  632. goto err_alloc;
  633. }
  634. device_initialize(&dev->dev);
  635. dev_set_name(&dev->dev, "%4.4lx", info->offset);
  636. dev->devid = info->devid;
  637. dev->dev.parent = sachip->dev;
  638. dev->dev.bus = &sa1111_bus_type;
  639. dev->dev.release = sa1111_dev_release;
  640. dev->res.start = sachip->phys + info->offset;
  641. dev->res.end = dev->res.start + 511;
  642. dev->res.name = dev_name(&dev->dev);
  643. dev->res.flags = IORESOURCE_MEM;
  644. dev->mapbase = sachip->base + info->offset;
  645. dev->skpcr_mask = info->skpcr_mask;
  646. for (i = 0; i < ARRAY_SIZE(info->hwirq); i++)
  647. dev->hwirq[i] = info->hwirq[i];
  648. /*
  649. * If the parent device has a DMA mask associated with it, and
  650. * this child supports DMA, propagate it down to the children.
  651. */
  652. if (info->dma && sachip->dev->dma_mask) {
  653. dev->dma_mask = *sachip->dev->dma_mask;
  654. dev->dev.dma_mask = &dev->dma_mask;
  655. dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask;
  656. }
  657. ret = request_resource(parent, &dev->res);
  658. if (ret) {
  659. dev_err(sachip->dev, "failed to allocate resource for %s\n",
  660. dev->res.name);
  661. goto err_resource;
  662. }
  663. ret = device_add(&dev->dev);
  664. if (ret)
  665. goto err_add;
  666. return 0;
  667. err_add:
  668. release_resource(&dev->res);
  669. err_resource:
  670. put_device(&dev->dev);
  671. err_alloc:
  672. return ret;
  673. }
  674. /**
  675. * sa1111_probe - probe for a single SA1111 chip.
  676. * @phys_addr: physical address of device.
  677. *
  678. * Probe for a SA1111 chip. This must be called
  679. * before any other SA1111-specific code.
  680. *
  681. * Returns:
  682. * %-ENODEV device not found.
  683. * %-EBUSY physical address already marked in-use.
  684. * %-EINVAL no platform data passed
  685. * %0 successful.
  686. */
  687. static int __sa1111_probe(struct device *me, struct resource *mem, int irq)
  688. {
  689. struct sa1111_platform_data *pd = me->platform_data;
  690. struct sa1111 *sachip;
  691. unsigned long id;
  692. unsigned int has_devs;
  693. int i, ret = -ENODEV;
  694. if (!pd)
  695. return -EINVAL;
  696. sachip = devm_kzalloc(me, sizeof(struct sa1111), GFP_KERNEL);
  697. if (!sachip)
  698. return -ENOMEM;
  699. sachip->clk = devm_clk_get(me, "SA1111_CLK");
  700. if (IS_ERR(sachip->clk))
  701. return PTR_ERR(sachip->clk);
  702. ret = clk_prepare(sachip->clk);
  703. if (ret)
  704. return ret;
  705. spin_lock_init(&sachip->lock);
  706. sachip->dev = me;
  707. dev_set_drvdata(sachip->dev, sachip);
  708. sachip->pdata = pd;
  709. sachip->phys = mem->start;
  710. sachip->irq = irq;
  711. /*
  712. * Map the whole region. This also maps the
  713. * registers for our children.
  714. */
  715. sachip->base = ioremap(mem->start, PAGE_SIZE * 2);
  716. if (!sachip->base) {
  717. ret = -ENOMEM;
  718. goto err_clk_unprep;
  719. }
  720. /*
  721. * Probe for the chip. Only touch the SBI registers.
  722. */
  723. id = readl_relaxed(sachip->base + SA1111_SKID);
  724. if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
  725. printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id);
  726. ret = -ENODEV;
  727. goto err_unmap;
  728. }
  729. pr_info("SA1111 Microprocessor Companion Chip: silicon revision %lx, metal revision %lx\n",
  730. (id & SKID_SIREV_MASK) >> 4, id & SKID_MTREV_MASK);
  731. /*
  732. * We found it. Wake the chip up, and initialise.
  733. */
  734. sa1111_wake(sachip);
  735. /*
  736. * The interrupt controller must be initialised before any
  737. * other device to ensure that the interrupts are available.
  738. */
  739. ret = sa1111_setup_irq(sachip, pd->irq_base);
  740. if (ret)
  741. goto err_clk;
  742. /* Setup the GPIOs - should really be done after the IRQ setup */
  743. ret = sa1111_setup_gpios(sachip);
  744. if (ret)
  745. goto err_irq;
  746. #ifdef CONFIG_ARCH_SA1100
  747. {
  748. unsigned int val;
  749. /*
  750. * The SDRAM configuration of the SA1110 and the SA1111 must
  751. * match. This is very important to ensure that SA1111 accesses
  752. * don't corrupt the SDRAM. Note that this ungates the SA1111's
  753. * MBGNT signal, so we must have called sa1110_mb_disable()
  754. * beforehand.
  755. */
  756. sa1111_configure_smc(sachip, 1,
  757. FExtr(MDCNFG, MDCNFG_SA1110_DRAC0),
  758. FExtr(MDCNFG, MDCNFG_SA1110_TDL0));
  759. /*
  760. * We only need to turn on DCLK whenever we want to use the
  761. * DMA. It can otherwise be held firmly in the off position.
  762. * (currently, we always enable it.)
  763. */
  764. val = readl_relaxed(sachip->base + SA1111_SKPCR);
  765. writel_relaxed(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR);
  766. /*
  767. * Enable the SA1110 memory bus request and grant signals.
  768. */
  769. sa1110_mb_enable();
  770. }
  771. #endif
  772. g_sa1111 = sachip;
  773. has_devs = ~0;
  774. if (pd)
  775. has_devs &= ~pd->disable_devs;
  776. for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++)
  777. if (sa1111_devices[i].devid & has_devs)
  778. sa1111_init_one_child(sachip, mem, &sa1111_devices[i]);
  779. return 0;
  780. err_irq:
  781. sa1111_remove_irq(sachip);
  782. err_clk:
  783. clk_disable(sachip->clk);
  784. err_unmap:
  785. iounmap(sachip->base);
  786. err_clk_unprep:
  787. clk_unprepare(sachip->clk);
  788. return ret;
  789. }
  790. static int sa1111_remove_one(struct device *dev, void *data)
  791. {
  792. struct sa1111_dev *sadev = to_sa1111_device(dev);
  793. if (dev->bus != &sa1111_bus_type)
  794. return 0;
  795. device_del(&sadev->dev);
  796. release_resource(&sadev->res);
  797. put_device(&sadev->dev);
  798. return 0;
  799. }
  800. static void __sa1111_remove(struct sa1111 *sachip)
  801. {
  802. device_for_each_child(sachip->dev, NULL, sa1111_remove_one);
  803. sa1111_remove_irq(sachip);
  804. clk_disable(sachip->clk);
  805. clk_unprepare(sachip->clk);
  806. iounmap(sachip->base);
  807. }
  808. struct sa1111_save_data {
  809. unsigned int skcr;
  810. unsigned int skpcr;
  811. unsigned int skcdr;
  812. unsigned char skaud;
  813. unsigned char skpwm0;
  814. unsigned char skpwm1;
  815. /*
  816. * Interrupt controller
  817. */
  818. unsigned int intpol0;
  819. unsigned int intpol1;
  820. unsigned int inten0;
  821. unsigned int inten1;
  822. unsigned int wakepol0;
  823. unsigned int wakepol1;
  824. unsigned int wakeen0;
  825. unsigned int wakeen1;
  826. };
  827. #ifdef CONFIG_PM
  828. static int sa1111_suspend_noirq(struct device *dev)
  829. {
  830. struct sa1111 *sachip = dev_get_drvdata(dev);
  831. struct sa1111_save_data *save;
  832. unsigned long flags;
  833. unsigned int val;
  834. void __iomem *base;
  835. save = kmalloc(sizeof(struct sa1111_save_data), GFP_KERNEL);
  836. if (!save)
  837. return -ENOMEM;
  838. sachip->saved_state = save;
  839. spin_lock_irqsave(&sachip->lock, flags);
  840. /*
  841. * Save state.
  842. */
  843. base = sachip->base;
  844. save->skcr = readl_relaxed(base + SA1111_SKCR);
  845. save->skpcr = readl_relaxed(base + SA1111_SKPCR);
  846. save->skcdr = readl_relaxed(base + SA1111_SKCDR);
  847. save->skaud = readl_relaxed(base + SA1111_SKAUD);
  848. save->skpwm0 = readl_relaxed(base + SA1111_SKPWM0);
  849. save->skpwm1 = readl_relaxed(base + SA1111_SKPWM1);
  850. writel_relaxed(0, sachip->base + SA1111_SKPWM0);
  851. writel_relaxed(0, sachip->base + SA1111_SKPWM1);
  852. base = sachip->base + SA1111_INTC;
  853. save->intpol0 = readl_relaxed(base + SA1111_INTPOL0);
  854. save->intpol1 = readl_relaxed(base + SA1111_INTPOL1);
  855. save->inten0 = readl_relaxed(base + SA1111_INTEN0);
  856. save->inten1 = readl_relaxed(base + SA1111_INTEN1);
  857. save->wakepol0 = readl_relaxed(base + SA1111_WAKEPOL0);
  858. save->wakepol1 = readl_relaxed(base + SA1111_WAKEPOL1);
  859. save->wakeen0 = readl_relaxed(base + SA1111_WAKEEN0);
  860. save->wakeen1 = readl_relaxed(base + SA1111_WAKEEN1);
  861. /*
  862. * Disable.
  863. */
  864. val = readl_relaxed(sachip->base + SA1111_SKCR);
  865. writel_relaxed(val | SKCR_SLEEP, sachip->base + SA1111_SKCR);
  866. clk_disable(sachip->clk);
  867. spin_unlock_irqrestore(&sachip->lock, flags);
  868. #ifdef CONFIG_ARCH_SA1100
  869. sa1110_mb_disable();
  870. #endif
  871. return 0;
  872. }
  873. /*
  874. * sa1111_resume - Restore the SA1111 device state.
  875. * @dev: device to restore
  876. *
  877. * Restore the general state of the SA1111; clock control and
  878. * interrupt controller. Other parts of the SA1111 must be
  879. * restored by their respective drivers, and must be called
  880. * via LDM after this function.
  881. */
  882. static int sa1111_resume_noirq(struct device *dev)
  883. {
  884. struct sa1111 *sachip = dev_get_drvdata(dev);
  885. struct sa1111_save_data *save;
  886. unsigned long flags, id;
  887. void __iomem *base;
  888. save = sachip->saved_state;
  889. if (!save)
  890. return 0;
  891. /*
  892. * Ensure that the SA1111 is still here.
  893. * FIXME: shouldn't do this here.
  894. */
  895. id = readl_relaxed(sachip->base + SA1111_SKID);
  896. if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
  897. __sa1111_remove(sachip);
  898. dev_set_drvdata(dev, NULL);
  899. kfree(save);
  900. return 0;
  901. }
  902. /*
  903. * First of all, wake up the chip.
  904. */
  905. sa1111_wake(sachip);
  906. #ifdef CONFIG_ARCH_SA1100
  907. /* Enable the memory bus request/grant signals */
  908. sa1110_mb_enable();
  909. #endif
  910. /*
  911. * Only lock for write ops. Also, sa1111_wake must be called with
  912. * released spinlock!
  913. */
  914. spin_lock_irqsave(&sachip->lock, flags);
  915. writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN0);
  916. writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN1);
  917. base = sachip->base;
  918. writel_relaxed(save->skcr, base + SA1111_SKCR);
  919. writel_relaxed(save->skpcr, base + SA1111_SKPCR);
  920. writel_relaxed(save->skcdr, base + SA1111_SKCDR);
  921. writel_relaxed(save->skaud, base + SA1111_SKAUD);
  922. writel_relaxed(save->skpwm0, base + SA1111_SKPWM0);
  923. writel_relaxed(save->skpwm1, base + SA1111_SKPWM1);
  924. base = sachip->base + SA1111_INTC;
  925. writel_relaxed(save->intpol0, base + SA1111_INTPOL0);
  926. writel_relaxed(save->intpol1, base + SA1111_INTPOL1);
  927. writel_relaxed(save->inten0, base + SA1111_INTEN0);
  928. writel_relaxed(save->inten1, base + SA1111_INTEN1);
  929. writel_relaxed(save->wakepol0, base + SA1111_WAKEPOL0);
  930. writel_relaxed(save->wakepol1, base + SA1111_WAKEPOL1);
  931. writel_relaxed(save->wakeen0, base + SA1111_WAKEEN0);
  932. writel_relaxed(save->wakeen1, base + SA1111_WAKEEN1);
  933. spin_unlock_irqrestore(&sachip->lock, flags);
  934. sachip->saved_state = NULL;
  935. kfree(save);
  936. return 0;
  937. }
  938. #else
  939. #define sa1111_suspend_noirq NULL
  940. #define sa1111_resume_noirq NULL
  941. #endif
  942. static int sa1111_probe(struct platform_device *pdev)
  943. {
  944. struct resource *mem;
  945. int irq;
  946. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  947. if (!mem)
  948. return -EINVAL;
  949. irq = platform_get_irq(pdev, 0);
  950. if (irq < 0)
  951. return irq;
  952. return __sa1111_probe(&pdev->dev, mem, irq);
  953. }
  954. static int sa1111_remove(struct platform_device *pdev)
  955. {
  956. struct sa1111 *sachip = platform_get_drvdata(pdev);
  957. if (sachip) {
  958. #ifdef CONFIG_PM
  959. kfree(sachip->saved_state);
  960. sachip->saved_state = NULL;
  961. #endif
  962. __sa1111_remove(sachip);
  963. platform_set_drvdata(pdev, NULL);
  964. }
  965. return 0;
  966. }
  967. static struct dev_pm_ops sa1111_pm_ops = {
  968. .suspend_noirq = sa1111_suspend_noirq,
  969. .resume_noirq = sa1111_resume_noirq,
  970. };
  971. /*
  972. * Not sure if this should be on the system bus or not yet.
  973. * We really want some way to register a system device at
  974. * the per-machine level, and then have this driver pick
  975. * up the registered devices.
  976. *
  977. * We also need to handle the SDRAM configuration for
  978. * PXA250/SA1110 machine classes.
  979. */
  980. static struct platform_driver sa1111_device_driver = {
  981. .probe = sa1111_probe,
  982. .remove = sa1111_remove,
  983. .driver = {
  984. .name = "sa1111",
  985. .pm = &sa1111_pm_ops,
  986. },
  987. };
  988. /*
  989. * Get the parent device driver (us) structure
  990. * from a child function device
  991. */
  992. static inline struct sa1111 *sa1111_chip_driver(struct sa1111_dev *sadev)
  993. {
  994. return (struct sa1111 *)dev_get_drvdata(sadev->dev.parent);
  995. }
  996. /*
  997. * The bits in the opdiv field are non-linear.
  998. */
  999. static unsigned char opdiv_table[] = { 1, 4, 2, 8 };
  1000. static unsigned int __sa1111_pll_clock(struct sa1111 *sachip)
  1001. {
  1002. unsigned int skcdr, fbdiv, ipdiv, opdiv;
  1003. skcdr = readl_relaxed(sachip->base + SA1111_SKCDR);
  1004. fbdiv = (skcdr & 0x007f) + 2;
  1005. ipdiv = ((skcdr & 0x0f80) >> 7) + 2;
  1006. opdiv = opdiv_table[(skcdr & 0x3000) >> 12];
  1007. return 3686400 * fbdiv / (ipdiv * opdiv);
  1008. }
  1009. /**
  1010. * sa1111_pll_clock - return the current PLL clock frequency.
  1011. * @sadev: SA1111 function block
  1012. *
  1013. * BUG: we should look at SKCR. We also blindly believe that
  1014. * the chip is being fed with the 3.6864MHz clock.
  1015. *
  1016. * Returns the PLL clock in Hz.
  1017. */
  1018. unsigned int sa1111_pll_clock(struct sa1111_dev *sadev)
  1019. {
  1020. struct sa1111 *sachip = sa1111_chip_driver(sadev);
  1021. return __sa1111_pll_clock(sachip);
  1022. }
  1023. EXPORT_SYMBOL(sa1111_pll_clock);
  1024. /**
  1025. * sa1111_select_audio_mode - select I2S or AC link mode
  1026. * @sadev: SA1111 function block
  1027. * @mode: One of %SA1111_AUDIO_ACLINK or %SA1111_AUDIO_I2S
  1028. *
  1029. * Frob the SKCR to select AC Link mode or I2S mode for
  1030. * the audio block.
  1031. */
  1032. void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode)
  1033. {
  1034. struct sa1111 *sachip = sa1111_chip_driver(sadev);
  1035. unsigned long flags;
  1036. unsigned int val;
  1037. spin_lock_irqsave(&sachip->lock, flags);
  1038. val = readl_relaxed(sachip->base + SA1111_SKCR);
  1039. if (mode == SA1111_AUDIO_I2S) {
  1040. val &= ~SKCR_SELAC;
  1041. } else {
  1042. val |= SKCR_SELAC;
  1043. }
  1044. writel_relaxed(val, sachip->base + SA1111_SKCR);
  1045. spin_unlock_irqrestore(&sachip->lock, flags);
  1046. }
  1047. EXPORT_SYMBOL(sa1111_select_audio_mode);
  1048. /**
  1049. * sa1111_set_audio_rate - set the audio sample rate
  1050. * @sadev: SA1111 SAC function block
  1051. * @rate: sample rate to select
  1052. */
  1053. int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate)
  1054. {
  1055. struct sa1111 *sachip = sa1111_chip_driver(sadev);
  1056. unsigned int div;
  1057. if (sadev->devid != SA1111_DEVID_SAC)
  1058. return -EINVAL;
  1059. div = (__sa1111_pll_clock(sachip) / 256 + rate / 2) / rate;
  1060. if (div == 0)
  1061. div = 1;
  1062. if (div > 128)
  1063. div = 128;
  1064. writel_relaxed(div - 1, sachip->base + SA1111_SKAUD);
  1065. return 0;
  1066. }
  1067. EXPORT_SYMBOL(sa1111_set_audio_rate);
  1068. /**
  1069. * sa1111_get_audio_rate - get the audio sample rate
  1070. * @sadev: SA1111 SAC function block device
  1071. */
  1072. int sa1111_get_audio_rate(struct sa1111_dev *sadev)
  1073. {
  1074. struct sa1111 *sachip = sa1111_chip_driver(sadev);
  1075. unsigned long div;
  1076. if (sadev->devid != SA1111_DEVID_SAC)
  1077. return -EINVAL;
  1078. div = readl_relaxed(sachip->base + SA1111_SKAUD) + 1;
  1079. return __sa1111_pll_clock(sachip) / (256 * div);
  1080. }
  1081. EXPORT_SYMBOL(sa1111_get_audio_rate);
  1082. /*
  1083. * Individual device operations.
  1084. */
  1085. /**
  1086. * sa1111_enable_device - enable an on-chip SA1111 function block
  1087. * @sadev: SA1111 function block device to enable
  1088. */
  1089. int sa1111_enable_device(struct sa1111_dev *sadev)
  1090. {
  1091. struct sa1111 *sachip = sa1111_chip_driver(sadev);
  1092. unsigned long flags;
  1093. unsigned int val;
  1094. int ret = 0;
  1095. if (sachip->pdata && sachip->pdata->enable)
  1096. ret = sachip->pdata->enable(sachip->pdata->data, sadev->devid);
  1097. if (ret == 0) {
  1098. spin_lock_irqsave(&sachip->lock, flags);
  1099. val = readl_relaxed(sachip->base + SA1111_SKPCR);
  1100. writel_relaxed(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
  1101. spin_unlock_irqrestore(&sachip->lock, flags);
  1102. }
  1103. return ret;
  1104. }
  1105. EXPORT_SYMBOL(sa1111_enable_device);
  1106. /**
  1107. * sa1111_disable_device - disable an on-chip SA1111 function block
  1108. * @sadev: SA1111 function block device to disable
  1109. */
  1110. void sa1111_disable_device(struct sa1111_dev *sadev)
  1111. {
  1112. struct sa1111 *sachip = sa1111_chip_driver(sadev);
  1113. unsigned long flags;
  1114. unsigned int val;
  1115. spin_lock_irqsave(&sachip->lock, flags);
  1116. val = readl_relaxed(sachip->base + SA1111_SKPCR);
  1117. writel_relaxed(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
  1118. spin_unlock_irqrestore(&sachip->lock, flags);
  1119. if (sachip->pdata && sachip->pdata->disable)
  1120. sachip->pdata->disable(sachip->pdata->data, sadev->devid);
  1121. }
  1122. EXPORT_SYMBOL(sa1111_disable_device);
  1123. int sa1111_get_irq(struct sa1111_dev *sadev, unsigned num)
  1124. {
  1125. struct sa1111 *sachip = sa1111_chip_driver(sadev);
  1126. if (num >= ARRAY_SIZE(sadev->hwirq))
  1127. return -EINVAL;
  1128. return sa1111_map_irq(sachip, sadev->hwirq[num]);
  1129. }
  1130. EXPORT_SYMBOL_GPL(sa1111_get_irq);
  1131. /*
  1132. * SA1111 "Register Access Bus."
  1133. *
  1134. * We model this as a regular bus type, and hang devices directly
  1135. * off this.
  1136. */
  1137. static int sa1111_match(struct device *_dev, struct device_driver *_drv)
  1138. {
  1139. struct sa1111_dev *dev = to_sa1111_device(_dev);
  1140. struct sa1111_driver *drv = SA1111_DRV(_drv);
  1141. return !!(dev->devid & drv->devid);
  1142. }
  1143. static int sa1111_bus_probe(struct device *dev)
  1144. {
  1145. struct sa1111_dev *sadev = to_sa1111_device(dev);
  1146. struct sa1111_driver *drv = SA1111_DRV(dev->driver);
  1147. int ret = -ENODEV;
  1148. if (drv->probe)
  1149. ret = drv->probe(sadev);
  1150. return ret;
  1151. }
  1152. static void sa1111_bus_remove(struct device *dev)
  1153. {
  1154. struct sa1111_dev *sadev = to_sa1111_device(dev);
  1155. struct sa1111_driver *drv = SA1111_DRV(dev->driver);
  1156. if (drv->remove)
  1157. drv->remove(sadev);
  1158. }
  1159. struct bus_type sa1111_bus_type = {
  1160. .name = "sa1111-rab",
  1161. .match = sa1111_match,
  1162. .probe = sa1111_bus_probe,
  1163. .remove = sa1111_bus_remove,
  1164. };
  1165. EXPORT_SYMBOL(sa1111_bus_type);
  1166. int sa1111_driver_register(struct sa1111_driver *driver)
  1167. {
  1168. driver->drv.bus = &sa1111_bus_type;
  1169. return driver_register(&driver->drv);
  1170. }
  1171. EXPORT_SYMBOL(sa1111_driver_register);
  1172. void sa1111_driver_unregister(struct sa1111_driver *driver)
  1173. {
  1174. driver_unregister(&driver->drv);
  1175. }
  1176. EXPORT_SYMBOL(sa1111_driver_unregister);
  1177. static int __init sa1111_init(void)
  1178. {
  1179. int ret = bus_register(&sa1111_bus_type);
  1180. if (ret == 0)
  1181. platform_driver_register(&sa1111_device_driver);
  1182. return ret;
  1183. }
  1184. static void __exit sa1111_exit(void)
  1185. {
  1186. platform_driver_unregister(&sa1111_device_driver);
  1187. bus_unregister(&sa1111_bus_type);
  1188. }
  1189. subsys_initcall(sa1111_init);
  1190. module_exit(sa1111_exit);
  1191. MODULE_DESCRIPTION("Intel Corporation SA1111 core driver");
  1192. MODULE_LICENSE("GPL");