zynq-zturn-common.dtsi 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2015 Andrea Merello <[email protected]>
  4. * Copyright (C) 2017 Alexander Graf <[email protected]>
  5. *
  6. * Based on zynq-zed.dts which is:
  7. * Copyright (C) 2011 - 2014 Xilinx
  8. * Copyright (C) 2012 National Instruments Corp.
  9. *
  10. */
  11. /dts-v1/;
  12. /include/ "zynq-7000.dtsi"
  13. / {
  14. compatible = "xlnx,zynq-7000";
  15. aliases {
  16. ethernet0 = &gem0;
  17. serial0 = &uart1;
  18. serial1 = &uart0;
  19. mmc0 = &sdhci0;
  20. };
  21. memory@0 {
  22. device_type = "memory";
  23. reg = <0x0 0x40000000>;
  24. };
  25. chosen {
  26. stdout-path = "serial0:115200n8";
  27. };
  28. gpio-leds {
  29. compatible = "gpio-leds";
  30. usr-led1 {
  31. label = "usr-led1";
  32. gpios = <&gpio0 0x0 0x1>;
  33. default-state = "off";
  34. };
  35. usr-led2 {
  36. label = "usr-led2";
  37. gpios = <&gpio0 0x9 0x1>;
  38. default-state = "off";
  39. };
  40. };
  41. gpio-keys {
  42. compatible = "gpio-keys";
  43. autorepeat;
  44. key {
  45. label = "K1";
  46. gpios = <&gpio0 0x32 0x1>;
  47. linux,code = <0x66>;
  48. wakeup-source;
  49. autorepeat;
  50. };
  51. };
  52. };
  53. &clkc {
  54. ps-clk-frequency = <33333333>;
  55. };
  56. &gem0 {
  57. status = "okay";
  58. phy-mode = "rgmii-id";
  59. phy-handle = <&ethernet_phy>;
  60. ethernet_phy: ethernet-phy@0 {
  61. };
  62. };
  63. &sdhci0 {
  64. status = "okay";
  65. };
  66. &uart0 {
  67. status = "okay";
  68. };
  69. &uart1 {
  70. status = "okay";
  71. };
  72. &usb0 {
  73. status = "okay";
  74. dr_mode = "host";
  75. };
  76. &can0 {
  77. status = "okay";
  78. };
  79. &i2c0 {
  80. status = "okay";
  81. clock-frequency = <400000>;
  82. stlm75@49 {
  83. status = "okay";
  84. compatible = "lm75";
  85. reg = <0x49>;
  86. };
  87. accelerometer@53 {
  88. compatible = "adi,adxl345";
  89. reg = <0x53>;
  90. interrupt-parent = <&intc>;
  91. interrupts = <0x0 0x1e 0x4>;
  92. };
  93. };