zynq-zc702.dts 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2011 - 2014 Xilinx
  4. * Copyright (C) 2012 National Instruments Corp.
  5. */
  6. /dts-v1/;
  7. #include "zynq-7000.dtsi"
  8. / {
  9. model = "Xilinx ZC702 board";
  10. compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
  11. aliases {
  12. ethernet0 = &gem0;
  13. i2c0 = &i2c0;
  14. serial0 = &uart1;
  15. mmc0 = &sdhci0;
  16. };
  17. memory@0 {
  18. device_type = "memory";
  19. reg = <0x0 0x40000000>;
  20. };
  21. chosen {
  22. bootargs = "";
  23. stdout-path = "serial0:115200n8";
  24. };
  25. gpio-keys {
  26. compatible = "gpio-keys";
  27. autorepeat;
  28. switch-14 {
  29. label = "sw14";
  30. gpios = <&gpio0 12 0>;
  31. linux,code = <108>; /* down */
  32. wakeup-source;
  33. autorepeat;
  34. };
  35. switch-13 {
  36. label = "sw13";
  37. gpios = <&gpio0 14 0>;
  38. linux,code = <103>; /* up */
  39. wakeup-source;
  40. autorepeat;
  41. };
  42. };
  43. leds {
  44. compatible = "gpio-leds";
  45. led-ds23 {
  46. label = "ds23";
  47. gpios = <&gpio0 10 0>;
  48. linux,default-trigger = "heartbeat";
  49. };
  50. };
  51. usb_phy0: phy0 {
  52. compatible = "usb-nop-xceiv";
  53. #phy-cells = <0>;
  54. };
  55. };
  56. &amba {
  57. ocm: sram@fffc0000 {
  58. compatible = "mmio-sram";
  59. reg = <0xfffc0000 0x10000>;
  60. #address-cells = <1>;
  61. #size-cells = <1>;
  62. ranges = <0 0xfffc0000 0x10000>;
  63. ocm-sram@0 {
  64. reg = <0x0 0x10000>;
  65. };
  66. };
  67. };
  68. &can0 {
  69. status = "okay";
  70. pinctrl-names = "default";
  71. pinctrl-0 = <&pinctrl_can0_default>;
  72. };
  73. &clkc {
  74. ps-clk-frequency = <33333333>;
  75. };
  76. &gem0 {
  77. status = "okay";
  78. phy-mode = "rgmii-id";
  79. phy-handle = <&ethernet_phy>;
  80. pinctrl-names = "default";
  81. pinctrl-0 = <&pinctrl_gem0_default>;
  82. ethernet_phy: ethernet-phy@7 {
  83. reg = <7>;
  84. device_type = "ethernet-phy";
  85. };
  86. };
  87. &gpio0 {
  88. pinctrl-names = "default";
  89. pinctrl-0 = <&pinctrl_gpio0_default>;
  90. };
  91. &i2c0 {
  92. status = "okay";
  93. clock-frequency = <400000>;
  94. pinctrl-names = "default";
  95. pinctrl-0 = <&pinctrl_i2c0_default>;
  96. i2c-mux@74 {
  97. compatible = "nxp,pca9548";
  98. #address-cells = <1>;
  99. #size-cells = <0>;
  100. reg = <0x74>;
  101. i2c@0 {
  102. #address-cells = <1>;
  103. #size-cells = <0>;
  104. reg = <0>;
  105. si570: clock-generator@5d {
  106. #clock-cells = <0>;
  107. compatible = "silabs,si570";
  108. temperature-stability = <50>;
  109. reg = <0x5d>;
  110. factory-fout = <156250000>;
  111. clock-frequency = <148500000>;
  112. };
  113. };
  114. i2c@1 {
  115. #address-cells = <1>;
  116. #size-cells = <0>;
  117. reg = <1>;
  118. adv7511: hdmi-tx@39 {
  119. compatible = "adi,adv7511";
  120. reg = <0x39>;
  121. adi,input-depth = <8>;
  122. adi,input-colorspace = "yuv422";
  123. adi,input-clock = "1x";
  124. adi,input-style = <3>;
  125. adi,input-justification = "right";
  126. };
  127. };
  128. i2c@2 {
  129. #address-cells = <1>;
  130. #size-cells = <0>;
  131. reg = <2>;
  132. eeprom@54 {
  133. compatible = "atmel,24c08";
  134. reg = <0x54>;
  135. };
  136. };
  137. i2c@3 {
  138. #address-cells = <1>;
  139. #size-cells = <0>;
  140. reg = <3>;
  141. gpio@21 {
  142. compatible = "ti,tca6416";
  143. reg = <0x21>;
  144. gpio-controller;
  145. #gpio-cells = <2>;
  146. };
  147. };
  148. i2c@4 {
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. reg = <4>;
  152. rtc@51 {
  153. compatible = "nxp,pcf8563";
  154. reg = <0x51>;
  155. };
  156. };
  157. i2c@7 {
  158. #address-cells = <1>;
  159. #size-cells = <0>;
  160. reg = <7>;
  161. hwmon@34 {
  162. compatible = "ti,ucd9248";
  163. reg = <0x34>;
  164. };
  165. hwmon@35 {
  166. compatible = "ti,ucd9248";
  167. reg = <0x35>;
  168. };
  169. hwmon@36 {
  170. compatible = "ti,ucd9248";
  171. reg = <0x36>;
  172. };
  173. };
  174. };
  175. };
  176. &pinctrl0 {
  177. pinctrl_can0_default: can0-default {
  178. mux {
  179. function = "can0";
  180. groups = "can0_9_grp";
  181. };
  182. conf {
  183. groups = "can0_9_grp";
  184. slew-rate = <0>;
  185. io-standard = <1>;
  186. };
  187. conf-rx {
  188. pins = "MIO46";
  189. bias-high-impedance;
  190. };
  191. conf-tx {
  192. pins = "MIO47";
  193. bias-disable;
  194. };
  195. };
  196. pinctrl_gem0_default: gem0-default {
  197. mux {
  198. function = "ethernet0";
  199. groups = "ethernet0_0_grp";
  200. };
  201. conf {
  202. groups = "ethernet0_0_grp";
  203. slew-rate = <0>;
  204. io-standard = <4>;
  205. };
  206. conf-rx {
  207. pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
  208. bias-high-impedance;
  209. low-power-disable;
  210. };
  211. conf-tx {
  212. pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
  213. bias-disable;
  214. low-power-enable;
  215. };
  216. mux-mdio {
  217. function = "mdio0";
  218. groups = "mdio0_0_grp";
  219. };
  220. conf-mdio {
  221. groups = "mdio0_0_grp";
  222. slew-rate = <0>;
  223. io-standard = <1>;
  224. bias-disable;
  225. };
  226. };
  227. pinctrl_gpio0_default: gpio0-default {
  228. mux {
  229. function = "gpio0";
  230. groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
  231. "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
  232. "gpio0_13_grp", "gpio0_14_grp";
  233. };
  234. conf {
  235. groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
  236. "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
  237. "gpio0_13_grp", "gpio0_14_grp";
  238. slew-rate = <0>;
  239. io-standard = <1>;
  240. };
  241. conf-pull-up {
  242. pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
  243. bias-pull-up;
  244. };
  245. conf-pull-none {
  246. pins = "MIO7", "MIO8";
  247. bias-disable;
  248. };
  249. };
  250. pinctrl_i2c0_default: i2c0-default {
  251. mux {
  252. groups = "i2c0_10_grp";
  253. function = "i2c0";
  254. };
  255. conf {
  256. groups = "i2c0_10_grp";
  257. bias-pull-up;
  258. slew-rate = <0>;
  259. io-standard = <1>;
  260. };
  261. };
  262. pinctrl_sdhci0_default: sdhci0-default {
  263. mux {
  264. groups = "sdio0_2_grp";
  265. function = "sdio0";
  266. };
  267. conf {
  268. groups = "sdio0_2_grp";
  269. slew-rate = <0>;
  270. io-standard = <1>;
  271. bias-disable;
  272. };
  273. mux-cd {
  274. groups = "gpio0_0_grp";
  275. function = "sdio0_cd";
  276. };
  277. conf-cd {
  278. groups = "gpio0_0_grp";
  279. bias-high-impedance;
  280. bias-pull-up;
  281. slew-rate = <0>;
  282. io-standard = <1>;
  283. };
  284. mux-wp {
  285. groups = "gpio0_15_grp";
  286. function = "sdio0_wp";
  287. };
  288. conf-wp {
  289. groups = "gpio0_15_grp";
  290. bias-high-impedance;
  291. bias-pull-up;
  292. slew-rate = <0>;
  293. io-standard = <1>;
  294. };
  295. };
  296. pinctrl_uart1_default: uart1-default {
  297. mux {
  298. groups = "uart1_10_grp";
  299. function = "uart1";
  300. };
  301. conf {
  302. groups = "uart1_10_grp";
  303. slew-rate = <0>;
  304. io-standard = <1>;
  305. };
  306. conf-rx {
  307. pins = "MIO49";
  308. bias-high-impedance;
  309. };
  310. conf-tx {
  311. pins = "MIO48";
  312. bias-disable;
  313. };
  314. };
  315. pinctrl_usb0_default: usb0-default {
  316. mux {
  317. groups = "usb0_0_grp";
  318. function = "usb0";
  319. };
  320. conf {
  321. groups = "usb0_0_grp";
  322. slew-rate = <0>;
  323. io-standard = <1>;
  324. };
  325. conf-rx {
  326. pins = "MIO29", "MIO31", "MIO36";
  327. bias-high-impedance;
  328. };
  329. conf-tx {
  330. pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
  331. "MIO35", "MIO37", "MIO38", "MIO39";
  332. bias-disable;
  333. };
  334. };
  335. };
  336. &sdhci0 {
  337. status = "okay";
  338. pinctrl-names = "default";
  339. pinctrl-0 = <&pinctrl_sdhci0_default>;
  340. };
  341. &uart1 {
  342. status = "okay";
  343. pinctrl-names = "default";
  344. pinctrl-0 = <&pinctrl_uart1_default>;
  345. };
  346. &usb0 {
  347. status = "okay";
  348. dr_mode = "host";
  349. usb-phy = <&usb_phy0>;
  350. pinctrl-names = "default";
  351. pinctrl-0 = <&pinctrl_usb0_default>;
  352. };