zynq-microzed.dts 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2011 - 2014 Xilinx
  4. * Copyright (C) 2016 Jagan Teki <[email protected]>
  5. */
  6. /dts-v1/;
  7. /include/ "zynq-7000.dtsi"
  8. / {
  9. model = "Avnet MicroZed board";
  10. compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
  11. aliases {
  12. ethernet0 = &gem0;
  13. serial0 = &uart1;
  14. };
  15. memory@0 {
  16. device_type = "memory";
  17. reg = <0x0 0x40000000>;
  18. };
  19. chosen {
  20. bootargs = "earlycon";
  21. stdout-path = "serial0:115200n8";
  22. };
  23. usb_phy0: phy0 {
  24. compatible = "usb-nop-xceiv";
  25. #phy-cells = <0>;
  26. };
  27. };
  28. &clkc {
  29. ps-clk-frequency = <33333333>;
  30. };
  31. &gem0 {
  32. status = "okay";
  33. phy-mode = "rgmii-id";
  34. phy-handle = <&ethernet_phy>;
  35. ethernet_phy: ethernet-phy@0 {
  36. reg = <0>;
  37. };
  38. };
  39. &sdhci0 {
  40. status = "okay";
  41. };
  42. &uart1 {
  43. status = "okay";
  44. };
  45. &usb0 {
  46. status = "okay";
  47. dr_mode = "host";
  48. usb-phy = <&usb_phy0>;
  49. pinctrl-names = "default";
  50. pinctrl-0 = <&pinctrl_usb0_default>;
  51. };
  52. &pinctrl0 {
  53. pinctrl_usb0_default: usb0-default {
  54. mux {
  55. groups = "usb0_0_grp";
  56. function = "usb0";
  57. };
  58. conf {
  59. groups = "usb0_0_grp";
  60. slew-rate = <0>;
  61. io-standard = <1>;
  62. };
  63. conf-rx {
  64. pins = "MIO29", "MIO31", "MIO36";
  65. bias-high-impedance;
  66. };
  67. conf-tx {
  68. pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
  69. "MIO35", "MIO37", "MIO38", "MIO39";
  70. bias-disable;
  71. };
  72. };
  73. };