zynq-ebaz4205.dts 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2021 Michael Walle <[email protected]>
  4. */
  5. /dts-v1/;
  6. /include/ "zynq-7000.dtsi"
  7. / {
  8. model = "Ebang EBAZ4205";
  9. compatible = "ebang,ebaz4205", "xlnx,zynq-7000";
  10. aliases {
  11. ethernet0 = &gem0;
  12. serial0 = &uart1;
  13. };
  14. memory@0 {
  15. device_type = "memory";
  16. reg = <0x0 0x10000000>;
  17. };
  18. chosen {
  19. stdout-path = "serial0:115200n8";
  20. };
  21. };
  22. &clkc {
  23. ps-clk-frequency = <33333333>;
  24. fclk-enable = <8>;
  25. };
  26. &gem0 {
  27. status = "okay";
  28. phy-mode = "mii";
  29. phy-handle = <&phy>;
  30. /* PHY clock */
  31. assigned-clocks = <&clkc 18>;
  32. assigned-clock-rates = <25000000>;
  33. phy: ethernet-phy@0 {
  34. reg = <0>;
  35. };
  36. };
  37. &gpio0 {
  38. pinctrl-names = "default";
  39. pinctrl-0 = <&pinctrl_gpio0_default>;
  40. };
  41. &nfc0 {
  42. status = "okay";
  43. nand@0 {
  44. reg = <0>;
  45. };
  46. };
  47. &pinctrl0 {
  48. pinctrl_gpio0_default: gpio0-default {
  49. mux {
  50. groups = "gpio0_20_grp", "gpio0_32_grp";
  51. function = "gpio0";
  52. };
  53. conf {
  54. groups = "gpio0_20_grp", "gpio0_32_grp";
  55. io-standard = <3>;
  56. slew-rate = <0>;
  57. };
  58. conf-pull-up {
  59. pins = "MIO20", "MIO32";
  60. bias-disable;
  61. };
  62. };
  63. pinctrl_sdhci0_default: sdhci0-default {
  64. mux {
  65. groups = "sdio0_2_grp";
  66. function = "sdio0";
  67. };
  68. conf {
  69. groups = "sdio0_2_grp";
  70. io-standard = <3>;
  71. slew-rate = <0>;
  72. bias-disable;
  73. };
  74. mux-cd {
  75. groups = "gpio0_34_grp";
  76. function = "sdio0_cd";
  77. };
  78. conf-cd {
  79. groups = "gpio0_34_grp";
  80. io-standard = <3>;
  81. slew-rate = <0>;
  82. bias-high-impedance;
  83. bias-pull-up;
  84. };
  85. };
  86. pinctrl_uart1_default: uart1-default {
  87. mux {
  88. groups = "uart1_4_grp";
  89. function = "uart1";
  90. };
  91. conf {
  92. groups = "uart1_4_grp";
  93. io-standard = <3>;
  94. slew-rate = <0>;
  95. };
  96. conf-rx {
  97. pins = "MIO25";
  98. bias-high-impedance;
  99. };
  100. conf-tx {
  101. pins = "MIO24";
  102. bias-disable;
  103. };
  104. };
  105. };
  106. &smcc {
  107. status = "okay";
  108. };
  109. &sdhci0 {
  110. status = "okay";
  111. disable-wp;
  112. pinctrl-names = "default";
  113. pinctrl-0 = <&pinctrl_sdhci0_default>;
  114. };
  115. &uart1 {
  116. status = "okay";
  117. pinctrl-names = "default";
  118. pinctrl-0 = <&pinctrl_uart1_default>;
  119. };