vf610-zii-scu4-aib.dts 15 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. //
  3. // Copyright (C) 2016-2018 Zodiac Inflight Innovations
  4. /dts-v1/;
  5. #include "vf610.dtsi"
  6. / {
  7. model = "ZII VF610 SCU4 AIB";
  8. compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610";
  9. chosen {
  10. stdout-path = &uart0;
  11. };
  12. memory@80000000 {
  13. device_type = "memory";
  14. reg = <0x80000000 0x20000000>;
  15. };
  16. gpio-leds {
  17. compatible = "gpio-leds";
  18. pinctrl-0 = <&pinctrl_leds_debug>;
  19. pinctrl-names = "default";
  20. debug {
  21. label = "zii:green:debug1";
  22. gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
  23. linux,default-trigger = "heartbeat";
  24. };
  25. };
  26. mdio-mux {
  27. compatible = "mdio-mux-gpio";
  28. pinctrl-0 = <&pinctrl_mdio_mux>;
  29. pinctrl-names = "default";
  30. gpios = <&gpio4 4 GPIO_ACTIVE_HIGH
  31. &gpio4 5 GPIO_ACTIVE_HIGH
  32. &gpio3 30 GPIO_ACTIVE_HIGH
  33. &gpio3 31 GPIO_ACTIVE_HIGH>;
  34. mdio-parent-bus = <&mdio1>;
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. mdio_mux_1: mdio@1 {
  38. reg = <1>;
  39. #address-cells = <1>;
  40. #size-cells = <0>;
  41. switch0: switch0@0 {
  42. compatible = "marvell,mv88e6190";
  43. reg = <0>;
  44. dsa,member = <0 0>;
  45. eeprom-length = <65536>;
  46. ports {
  47. #address-cells = <1>;
  48. #size-cells = <0>;
  49. port@0 {
  50. reg = <0>;
  51. label = "cpu";
  52. ethernet = <&fec1>;
  53. fixed-link {
  54. speed = <100>;
  55. full-duplex;
  56. };
  57. };
  58. port@1 {
  59. reg = <1>;
  60. label = "aib2main_1";
  61. };
  62. port@2 {
  63. reg = <2>;
  64. label = "aib2main_2";
  65. };
  66. port@3 {
  67. reg = <3>;
  68. label = "eth_cu_1000_5";
  69. };
  70. port@4 {
  71. reg = <4>;
  72. label = "eth_cu_1000_6";
  73. };
  74. port@5 {
  75. reg = <5>;
  76. label = "eth_cu_1000_4";
  77. };
  78. port@6 {
  79. reg = <6>;
  80. label = "eth_cu_1000_7";
  81. };
  82. port@7 {
  83. reg = <7>;
  84. label = "modem_pic";
  85. fixed-link {
  86. speed = <100>;
  87. full-duplex;
  88. };
  89. };
  90. switch0port10: port@10 {
  91. reg = <10>;
  92. label = "dsa";
  93. phy-mode = "xgmii";
  94. link = <&switch1port10
  95. &switch3port10
  96. &switch2port10>;
  97. };
  98. };
  99. };
  100. };
  101. mdio_mux_2: mdio@2 {
  102. reg = <2>;
  103. #address-cells = <1>;
  104. #size-cells = <0>;
  105. switch1: switch1@0 {
  106. compatible = "marvell,mv88e6190";
  107. reg = <0>;
  108. dsa,member = <0 1>;
  109. eeprom-length = <65536>;
  110. ports {
  111. #address-cells = <1>;
  112. #size-cells = <0>;
  113. port@1 {
  114. reg = <1>;
  115. label = "eth_cu_1000_3";
  116. };
  117. port@2 {
  118. reg = <2>;
  119. label = "eth_cu_100_2";
  120. };
  121. port@3 {
  122. reg = <3>;
  123. label = "eth_cu_100_3";
  124. };
  125. switch1port9: port@9 {
  126. reg = <9>;
  127. label = "dsa";
  128. phy-mode = "xgmii";
  129. link = <&switch3port10
  130. &switch2port10>;
  131. };
  132. switch1port10: port@10 {
  133. reg = <10>;
  134. label = "dsa";
  135. phy-mode = "xgmii";
  136. link = <&switch0port10>;
  137. };
  138. };
  139. };
  140. };
  141. mdio_mux_4: mdio@4 {
  142. reg = <4>;
  143. #address-cells = <1>;
  144. #size-cells = <0>;
  145. switch2: switch2@0 {
  146. compatible = "marvell,mv88e6190";
  147. reg = <0>;
  148. dsa,member = <0 2>;
  149. eeprom-length = <65536>;
  150. ports {
  151. #address-cells = <1>;
  152. #size-cells = <0>;
  153. port@2 {
  154. reg = <2>;
  155. label = "eth_fc_1000_2";
  156. phy-mode = "1000base-x";
  157. managed = "in-band-status";
  158. sfp = <&sff1>;
  159. };
  160. port@3 {
  161. reg = <3>;
  162. label = "eth_fc_1000_3";
  163. phy-mode = "1000base-x";
  164. managed = "in-band-status";
  165. sfp = <&sff2>;
  166. };
  167. port@4 {
  168. reg = <4>;
  169. label = "eth_fc_1000_4";
  170. phy-mode = "1000base-x";
  171. managed = "in-band-status";
  172. sfp = <&sff3>;
  173. };
  174. port@5 {
  175. reg = <5>;
  176. label = "eth_fc_1000_5";
  177. phy-mode = "1000base-x";
  178. managed = "in-band-status";
  179. sfp = <&sff4>;
  180. };
  181. port@6 {
  182. reg = <6>;
  183. label = "eth_fc_1000_6";
  184. phy-mode = "1000base-x";
  185. managed = "in-band-status";
  186. sfp = <&sff5>;
  187. };
  188. port@7 {
  189. reg = <7>;
  190. label = "eth_fc_1000_7";
  191. phy-mode = "1000base-x";
  192. managed = "in-band-status";
  193. sfp = <&sff6>;
  194. };
  195. port@9 {
  196. reg = <9>;
  197. label = "eth_fc_1000_1";
  198. phy-mode = "1000base-x";
  199. managed = "in-band-status";
  200. sfp = <&sff0>;
  201. };
  202. switch2port10: port@10 {
  203. reg = <10>;
  204. label = "dsa";
  205. phy-mode = "2500base-x";
  206. link = <&switch3port9
  207. &switch1port9
  208. &switch0port10>;
  209. };
  210. };
  211. };
  212. };
  213. mdio_mux_8: mdio@8 {
  214. reg = <8>;
  215. #address-cells = <1>;
  216. #size-cells = <0>;
  217. switch3: switch3@0 {
  218. compatible = "marvell,mv88e6190";
  219. reg = <0>;
  220. dsa,member = <0 3>;
  221. eeprom-length = <65536>;
  222. ports {
  223. #address-cells = <1>;
  224. #size-cells = <0>;
  225. port@2 {
  226. reg = <2>;
  227. label = "eth_fc_1000_8";
  228. phy-mode = "1000base-x";
  229. managed = "in-band-status";
  230. sfp = <&sff7>;
  231. };
  232. port@3 {
  233. reg = <3>;
  234. label = "eth_fc_1000_9";
  235. phy-mode = "1000base-x";
  236. managed = "in-band-status";
  237. sfp = <&sff8>;
  238. };
  239. port@4 {
  240. reg = <4>;
  241. label = "eth_fc_1000_10";
  242. phy-mode = "1000base-x";
  243. managed = "in-band-status";
  244. sfp = <&sff9>;
  245. };
  246. switch3port9: port@9 {
  247. reg = <9>;
  248. label = "dsa";
  249. phy-mode = "2500base-x";
  250. link = <&switch2port10>;
  251. };
  252. switch3port10: port@10 {
  253. reg = <10>;
  254. label = "dsa";
  255. phy-mode = "xgmii";
  256. link = <&switch1port9
  257. &switch0port10>;
  258. };
  259. };
  260. };
  261. };
  262. };
  263. sff0: sff0 {
  264. compatible = "sff,sff";
  265. i2c-bus = <&sff0_i2c>;
  266. los-gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>;
  267. tx-disable-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
  268. };
  269. sff1: sff1 {
  270. compatible = "sff,sff";
  271. i2c-bus = <&sff1_i2c>;
  272. los-gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>;
  273. tx-disable-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
  274. };
  275. sff2: sff2 {
  276. compatible = "sff,sff";
  277. i2c-bus = <&sff2_i2c>;
  278. los-gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
  279. tx-disable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
  280. };
  281. sff3: sff3 {
  282. compatible = "sff,sff";
  283. i2c-bus = <&sff3_i2c>;
  284. los-gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
  285. tx-disable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
  286. };
  287. sff4: sff4 {
  288. compatible = "sff,sff";
  289. i2c-bus = <&sff4_i2c>;
  290. los-gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
  291. tx-disable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
  292. };
  293. sff5: sff5 {
  294. compatible = "sff,sff";
  295. i2c-bus = <&sff5_i2c>;
  296. los-gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
  297. tx-disable-gpios = <&gpio7 5 GPIO_ACTIVE_HIGH>;
  298. };
  299. sff6: sff6 {
  300. compatible = "sff,sff";
  301. i2c-bus = <&sff6_i2c>;
  302. los-gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>;
  303. tx-disable-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
  304. };
  305. sff7: sff7 {
  306. compatible = "sff,sff";
  307. i2c-bus = <&sff7_i2c>;
  308. los-gpios = <&gpio9 7 GPIO_ACTIVE_HIGH>;
  309. tx-disable-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>;
  310. };
  311. sff8: sff8 {
  312. compatible = "sff,sff";
  313. i2c-bus = <&sff8_i2c>;
  314. los-gpios = <&gpio9 8 GPIO_ACTIVE_HIGH>;
  315. tx-disable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
  316. };
  317. sff9: sff9 {
  318. compatible = "sff,sff";
  319. i2c-bus = <&sff9_i2c>;
  320. los-gpios = <&gpio9 9 GPIO_ACTIVE_HIGH>;
  321. tx-disable-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
  322. };
  323. reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
  324. compatible = "regulator-fixed";
  325. regulator-name = "vcc_3v3_mcu";
  326. regulator-min-microvolt = <3300000>;
  327. regulator-max-microvolt = <3300000>;
  328. };
  329. };
  330. &dspi0 {
  331. pinctrl-0 = <&pinctrl_dspi0>;
  332. pinctrl-names = "default";
  333. bus-num = <0>;
  334. status = "okay";
  335. adc@5 {
  336. compatible = "holt,hi8435";
  337. reg = <5>;
  338. gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
  339. spi-max-frequency = <1000000>;
  340. };
  341. };
  342. &dspi1 {
  343. bus-num = <1>;
  344. pinctrl-names = "default";
  345. pinctrl-0 = <&pinctrl_dspi1>;
  346. status = "okay";
  347. flash@0 {
  348. #address-cells = <1>;
  349. #size-cells = <1>;
  350. compatible = "jedec,spi-nor";
  351. reg = <0>;
  352. spi-max-frequency = <50000000>;
  353. partition@0 {
  354. label = "m25p128-0";
  355. reg = <0x0 0x01000000>;
  356. };
  357. };
  358. flash@1 {
  359. #address-cells = <1>;
  360. #size-cells = <1>;
  361. compatible = "jedec,spi-nor";
  362. reg = <1>;
  363. spi-max-frequency = <50000000>;
  364. partition@0 {
  365. label = "m25p128-1";
  366. reg = <0x0 0x01000000>;
  367. };
  368. };
  369. };
  370. &adc0 {
  371. vref-supply = <&reg_vcc_3v3_mcu>;
  372. status = "okay";
  373. };
  374. &adc1 {
  375. vref-supply = <&reg_vcc_3v3_mcu>;
  376. status = "okay";
  377. };
  378. &edma0 {
  379. status = "okay";
  380. };
  381. &edma1 {
  382. status = "okay";
  383. };
  384. &esdhc0 {
  385. pinctrl-names = "default";
  386. pinctrl-0 = <&pinctrl_esdhc0>;
  387. bus-width = <8>;
  388. non-removable;
  389. no-1-8-v;
  390. no-sd;
  391. no-sdio;
  392. keep-power-in-suspend;
  393. status = "okay";
  394. };
  395. &esdhc1 {
  396. pinctrl-names = "default";
  397. pinctrl-0 = <&pinctrl_esdhc1>;
  398. bus-width = <4>;
  399. no-sdio;
  400. status = "okay";
  401. };
  402. &fec1 {
  403. phy-mode = "rmii";
  404. pinctrl-names = "default";
  405. pinctrl-0 = <&pinctrl_fec1>;
  406. status = "okay";
  407. fixed-link {
  408. speed = <100>;
  409. full-duplex;
  410. };
  411. mdio1: mdio {
  412. #address-cells = <1>;
  413. #size-cells = <0>;
  414. };
  415. };
  416. &i2c0 {
  417. clock-frequency = <100000>;
  418. pinctrl-names = "default";
  419. pinctrl-0 = <&pinctrl_i2c0>;
  420. status = "okay";
  421. gpio5: io-expander@20 {
  422. compatible = "nxp,pca9554";
  423. reg = <0x20>;
  424. gpio-controller;
  425. #gpio-cells = <2>;
  426. };
  427. gpio6: io-expander@22 {
  428. compatible = "nxp,pca9554";
  429. reg = <0x22>;
  430. gpio-controller;
  431. #gpio-cells = <2>;
  432. };
  433. temp-sensor@48 {
  434. compatible = "national,lm75";
  435. reg = <0x48>;
  436. };
  437. eeprom@50 {
  438. compatible = "atmel,24c04";
  439. reg = <0x50>;
  440. };
  441. eeprom@52 {
  442. compatible = "atmel,24c04";
  443. reg = <0x52>;
  444. };
  445. elapsed-time-recorder@6b {
  446. compatible = "dallas,ds1682";
  447. reg = <0x6b>;
  448. };
  449. };
  450. &i2c1 {
  451. clock-frequency = <100000>;
  452. pinctrl-names = "default";
  453. pinctrl-0 = <&pinctrl_i2c1>;
  454. status = "okay";
  455. watchdog@38 {
  456. compatible = "zii,rave-wdt";
  457. reg = <0x38>;
  458. };
  459. adc@4a {
  460. compatible = "adi,adt7411";
  461. reg = <0x4a>;
  462. };
  463. };
  464. &i2c2 {
  465. clock-frequency = <100000>;
  466. pinctrl-names = "default";
  467. pinctrl-0 = <&pinctrl_i2c2>;
  468. status = "okay";
  469. gpio9: io-expander@20 {
  470. compatible = "semtech,sx1503q";
  471. pinctrl-names = "default";
  472. pinctrl-0 = <&pinctrl_sx1503_20>;
  473. #gpio-cells = <2>;
  474. reg = <0x20>;
  475. gpio-controller;
  476. interrupt-parent = <&gpio1>;
  477. interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
  478. };
  479. temp-sensor@4e {
  480. compatible = "national,lm75";
  481. reg = <0x4e>;
  482. };
  483. temp-sensor@4f {
  484. compatible = "national,lm75";
  485. reg = <0x4f>;
  486. };
  487. gpio7: io-expander@23 {
  488. compatible = "nxp,pca9555";
  489. gpio-controller;
  490. #gpio-cells = <2>;
  491. reg = <0x23>;
  492. };
  493. adc@4a {
  494. compatible = "adi,adt7411";
  495. reg = <0x4a>;
  496. };
  497. eeprom@54 {
  498. compatible = "atmel,24c08";
  499. reg = <0x54>;
  500. };
  501. i2c-mux@70 {
  502. compatible = "nxp,pca9548";
  503. pinctrl-names = "default";
  504. #address-cells = <1>;
  505. #size-cells = <0>;
  506. reg = <0x70>;
  507. i2c-mux-idle-disconnect;
  508. sff0_i2c: i2c@1 {
  509. #address-cells = <1>;
  510. #size-cells = <0>;
  511. reg = <1>;
  512. };
  513. sff1_i2c: i2c@2 {
  514. #address-cells = <1>;
  515. #size-cells = <0>;
  516. reg = <2>;
  517. };
  518. sff2_i2c: i2c@3 {
  519. #address-cells = <1>;
  520. #size-cells = <0>;
  521. reg = <3>;
  522. };
  523. sff3_i2c: i2c@4 {
  524. #address-cells = <1>;
  525. #size-cells = <0>;
  526. reg = <4>;
  527. };
  528. sff4_i2c: i2c@5 {
  529. #address-cells = <1>;
  530. #size-cells = <0>;
  531. reg = <5>;
  532. };
  533. };
  534. i2c-mux@71 {
  535. compatible = "nxp,pca9548";
  536. pinctrl-names = "default";
  537. reg = <0x71>;
  538. #address-cells = <1>;
  539. #size-cells = <0>;
  540. i2c-mux-idle-disconnect;
  541. sff5_i2c: i2c@1 {
  542. #address-cells = <1>;
  543. #size-cells = <0>;
  544. reg = <1>;
  545. };
  546. sff6_i2c: i2c@2 {
  547. #address-cells = <1>;
  548. #size-cells = <0>;
  549. reg = <2>;
  550. };
  551. sff7_i2c: i2c@3 {
  552. #address-cells = <1>;
  553. #size-cells = <0>;
  554. reg = <3>;
  555. };
  556. sff8_i2c: i2c@4 {
  557. #address-cells = <1>;
  558. #size-cells = <0>;
  559. reg = <4>;
  560. };
  561. sff9_i2c: i2c@5 {
  562. #address-cells = <1>;
  563. #size-cells = <0>;
  564. reg = <5>;
  565. };
  566. };
  567. };
  568. &snvsrtc {
  569. status = "disabled";
  570. };
  571. &uart0 {
  572. pinctrl-names = "default";
  573. pinctrl-0 = <&pinctrl_uart0>;
  574. status = "okay";
  575. };
  576. &uart1 {
  577. linux,rs485-enabled-at-boot-time;
  578. pinctrl-names = "default";
  579. pinctrl-0 = <&pinctrl_uart1>;
  580. status = "okay";
  581. };
  582. &uart2 {
  583. linux,rs485-enabled-at-boot-time;
  584. pinctrl-names = "default";
  585. pinctrl-0 = <&pinctrl_uart2>;
  586. status = "okay";
  587. };
  588. &iomuxc {
  589. pinctrl_dspi0: dspi0grp {
  590. fsl,pins = <
  591. VF610_PAD_PTB19__DSPI0_CS0 0x1182
  592. VF610_PAD_PTB18__DSPI0_CS1 0x1182
  593. VF610_PAD_PTB13__DSPI0_CS4 0x1182
  594. VF610_PAD_PTB12__DSPI0_CS5 0x1182
  595. VF610_PAD_PTB20__DSPI0_SIN 0x1181
  596. VF610_PAD_PTB21__DSPI0_SOUT 0x1182
  597. VF610_PAD_PTB22__DSPI0_SCK 0x1182
  598. >;
  599. };
  600. pinctrl_dspi1: dspi1grp {
  601. fsl,pins = <
  602. VF610_PAD_PTD5__DSPI1_CS0 0x1182
  603. VF610_PAD_PTD4__DSPI1_CS1 0x1182
  604. VF610_PAD_PTC6__DSPI1_SIN 0x1181
  605. VF610_PAD_PTC7__DSPI1_SOUT 0x1182
  606. VF610_PAD_PTC8__DSPI1_SCK 0x1182
  607. >;
  608. };
  609. pinctrl_dspi2: dspi2gpio {
  610. fsl,pins = <
  611. VF610_PAD_PTD30__GPIO_64 0x33e2
  612. VF610_PAD_PTD29__GPIO_65 0x33e1
  613. VF610_PAD_PTD28__GPIO_66 0x33e2
  614. VF610_PAD_PTD27__GPIO_67 0x33e2
  615. VF610_PAD_PTD26__GPIO_68 0x31c2
  616. >;
  617. };
  618. pinctrl_esdhc0: esdhc0grp {
  619. fsl,pins = <
  620. VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
  621. VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
  622. VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
  623. VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
  624. VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
  625. VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
  626. VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
  627. VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
  628. VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
  629. VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
  630. >;
  631. };
  632. pinctrl_esdhc1: esdhc1grp {
  633. fsl,pins = <
  634. VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
  635. VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
  636. VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
  637. VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
  638. VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
  639. VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
  640. >;
  641. };
  642. pinctrl_fec1: fec1grp {
  643. fsl,pins = <
  644. VF610_PAD_PTA6__RMII_CLKIN 0x30d1
  645. VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
  646. VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
  647. VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
  648. VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
  649. VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
  650. VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
  651. VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
  652. VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
  653. VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
  654. >;
  655. };
  656. pinctrl_i2c0: i2c0grp {
  657. fsl,pins = <
  658. VF610_PAD_PTB14__I2C0_SCL 0x37ff
  659. VF610_PAD_PTB15__I2C0_SDA 0x37ff
  660. >;
  661. };
  662. pinctrl_i2c1: i2c1grp {
  663. fsl,pins = <
  664. VF610_PAD_PTB16__I2C1_SCL 0x37ff
  665. VF610_PAD_PTB17__I2C1_SDA 0x37ff
  666. >;
  667. };
  668. pinctrl_i2c2: i2c2grp {
  669. fsl,pins = <
  670. VF610_PAD_PTA22__I2C2_SCL 0x37ff
  671. VF610_PAD_PTA23__I2C2_SDA 0x37ff
  672. >;
  673. };
  674. pinctrl_leds_debug: pinctrl-leds-debug {
  675. fsl,pins = <
  676. VF610_PAD_PTB26__GPIO_96 0x31c2
  677. >;
  678. };
  679. pinctrl_mdio_mux: pinctrl-mdio-mux {
  680. fsl,pins = <
  681. VF610_PAD_PTE27__GPIO_132 0x31c2
  682. VF610_PAD_PTE28__GPIO_133 0x31c2
  683. VF610_PAD_PTE21__GPIO_126 0x31c2
  684. VF610_PAD_PTE22__GPIO_127 0x31c2
  685. >;
  686. };
  687. pinctrl_qspi0: qspi0grp {
  688. fsl,pins = <
  689. VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3
  690. VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff
  691. VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3
  692. VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3
  693. VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3
  694. VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3
  695. >;
  696. };
  697. pinctrl_sx1503_20: pinctrl-sx1503-20 {
  698. fsl,pins = <
  699. VF610_PAD_PTD31__GPIO_63 0x219d
  700. >;
  701. };
  702. pinctrl_uart0: uart0grp {
  703. fsl,pins = <
  704. VF610_PAD_PTB10__UART0_TX 0x21a2
  705. VF610_PAD_PTB11__UART0_RX 0x21a1
  706. >;
  707. };
  708. pinctrl_uart1: uart1grp {
  709. fsl,pins = <
  710. VF610_PAD_PTB23__UART1_TX 0x21a2
  711. VF610_PAD_PTB24__UART1_RX 0x21a1
  712. VF610_PAD_PTB25__UART1_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */
  713. >;
  714. };
  715. pinctrl_uart2: uart2grp {
  716. fsl,pins = <
  717. VF610_PAD_PTD0__UART2_TX 0x21a2
  718. VF610_PAD_PTD1__UART2_RX 0x21a1
  719. VF610_PAD_PTD2__UART2_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */
  720. >;
  721. };
  722. };