vf-colibri.dtsi 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR MIT
  2. /*
  3. * Copyright 2014-2020 Toradex
  4. *
  5. */
  6. / {
  7. aliases {
  8. ethernet0 = &fec1;
  9. ethernet1 = &fec0;
  10. };
  11. bl: backlight {
  12. compatible = "pwm-backlight";
  13. pinctrl-names = "default";
  14. pinctrl-0 = <&pinctrl_gpio_bl_on>;
  15. pwms = <&pwm0 0 5000000 0>;
  16. enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  17. status = "disabled";
  18. };
  19. reg_module_3v3: regulator-module-3v3 {
  20. compatible = "regulator-fixed";
  21. regulator-name = "+V3.3";
  22. regulator-min-microvolt = <3300000>;
  23. regulator-max-microvolt = <3300000>;
  24. };
  25. reg_module_3v3_avdd: regulator-module-3v3-avdd {
  26. compatible = "regulator-fixed";
  27. regulator-name = "+V3.3_AVDD_AUDIO";
  28. regulator-min-microvolt = <3300000>;
  29. regulator-max-microvolt = <3300000>;
  30. };
  31. };
  32. &adc0 {
  33. status = "okay";
  34. vref-supply = <&reg_module_3v3_avdd>;
  35. };
  36. &adc1 {
  37. status = "okay";
  38. vref-supply = <&reg_module_3v3_avdd>;
  39. };
  40. &can0 {
  41. pinctrl-names = "default";
  42. pinctrl-0 = <&pinctrl_flexcan0>;
  43. status = "disabled";
  44. };
  45. &can1 {
  46. pinctrl-names = "default";
  47. pinctrl-0 = <&pinctrl_flexcan1>;
  48. status = "disabled";
  49. };
  50. &clks {
  51. assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
  52. <&clks VF610_CLK_ENET_TS_SEL>;
  53. assigned-clock-parents = <&clks VF610_CLK_ENET_50M>,
  54. <&clks VF610_CLK_ENET_50M>;
  55. };
  56. &dspi1 {
  57. bus-num = <1>;
  58. pinctrl-names = "default";
  59. pinctrl-0 = <&pinctrl_dspi1>;
  60. };
  61. &edma0 {
  62. status = "okay";
  63. };
  64. &edma1 {
  65. status = "okay";
  66. };
  67. &esdhc1 {
  68. pinctrl-names = "default";
  69. pinctrl-0 = <&pinctrl_esdhc1>;
  70. bus-width = <4>;
  71. cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
  72. disable-wp;
  73. };
  74. &fec1 {
  75. phy-mode = "rmii";
  76. phy-supply = <&reg_module_3v3>;
  77. pinctrl-names = "default";
  78. pinctrl-0 = <&pinctrl_fec1>;
  79. };
  80. &i2c0 {
  81. clock-frequency = <400000>;
  82. pinctrl-names = "default", "gpio";
  83. pinctrl-0 = <&pinctrl_i2c0>;
  84. pinctrl-1 = <&pinctrl_i2c0_gpio>;
  85. scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  86. sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  87. };
  88. &nfc {
  89. pinctrl-names = "default";
  90. pinctrl-0 = <&pinctrl_nfc>;
  91. status = "okay";
  92. nand@0 {
  93. compatible = "fsl,vf610-nfc-nandcs";
  94. reg = <0>;
  95. #address-cells = <1>;
  96. #size-cells = <1>;
  97. nand-bus-width = <8>;
  98. nand-ecc-mode = "hw";
  99. nand-ecc-strength = <32>;
  100. nand-ecc-step-size = <2048>;
  101. nand-on-flash-bbt;
  102. };
  103. };
  104. &pwm0 {
  105. pinctrl-names = "default";
  106. pinctrl-0 = <&pinctrl_pwm0>;
  107. };
  108. &pwm1 {
  109. pinctrl-names = "default";
  110. pinctrl-0 = <&pinctrl_pwm1>;
  111. };
  112. &uart0 {
  113. pinctrl-names = "default";
  114. pinctrl-0 = <&pinctrl_uart0>;
  115. };
  116. &uart1 {
  117. pinctrl-names = "default";
  118. pinctrl-0 = <&pinctrl_uart1>;
  119. };
  120. &uart2 {
  121. pinctrl-names = "default";
  122. pinctrl-0 = <&pinctrl_uart2>;
  123. };
  124. &usbdev0 {
  125. disable-over-current;
  126. status = "okay";
  127. };
  128. &usbh1 {
  129. disable-over-current;
  130. status = "okay";
  131. };
  132. &usbmisc0 {
  133. status = "okay";
  134. };
  135. &usbmisc1 {
  136. status = "okay";
  137. };
  138. &usbphy0 {
  139. status = "okay";
  140. };
  141. &usbphy1 {
  142. status = "okay";
  143. };
  144. &iomuxc {
  145. vf610-colibri {
  146. pinctrl_flexcan0: can0grp {
  147. fsl,pins = <
  148. VF610_PAD_PTB14__CAN0_RX 0x31F1
  149. VF610_PAD_PTB15__CAN0_TX 0x31F2
  150. >;
  151. };
  152. pinctrl_flexcan1: can1grp {
  153. fsl,pins = <
  154. VF610_PAD_PTB16__CAN1_RX 0x31F1
  155. VF610_PAD_PTB17__CAN1_TX 0x31F2
  156. >;
  157. };
  158. pinctrl_gpio_ext: gpio_ext {
  159. fsl,pins = <
  160. VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */
  161. VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */
  162. VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */
  163. >;
  164. };
  165. pinctrl_dcu0_1: dcu0grp_1 {
  166. fsl,pins = <
  167. VF610_PAD_PTE0__DCU0_HSYNC 0x1902
  168. VF610_PAD_PTE1__DCU0_VSYNC 0x1902
  169. VF610_PAD_PTE2__DCU0_PCLK 0x1902
  170. VF610_PAD_PTE4__DCU0_DE 0x1902
  171. VF610_PAD_PTE5__DCU0_R0 0x1902
  172. VF610_PAD_PTE6__DCU0_R1 0x1902
  173. VF610_PAD_PTE7__DCU0_R2 0x1902
  174. VF610_PAD_PTE8__DCU0_R3 0x1902
  175. VF610_PAD_PTE9__DCU0_R4 0x1902
  176. VF610_PAD_PTE10__DCU0_R5 0x1902
  177. VF610_PAD_PTE11__DCU0_R6 0x1902
  178. VF610_PAD_PTE12__DCU0_R7 0x1902
  179. VF610_PAD_PTE13__DCU0_G0 0x1902
  180. VF610_PAD_PTE14__DCU0_G1 0x1902
  181. VF610_PAD_PTE15__DCU0_G2 0x1902
  182. VF610_PAD_PTE16__DCU0_G3 0x1902
  183. VF610_PAD_PTE17__DCU0_G4 0x1902
  184. VF610_PAD_PTE18__DCU0_G5 0x1902
  185. VF610_PAD_PTE19__DCU0_G6 0x1902
  186. VF610_PAD_PTE20__DCU0_G7 0x1902
  187. VF610_PAD_PTE21__DCU0_B0 0x1902
  188. VF610_PAD_PTE22__DCU0_B1 0x1902
  189. VF610_PAD_PTE23__DCU0_B2 0x1902
  190. VF610_PAD_PTE24__DCU0_B3 0x1902
  191. VF610_PAD_PTE25__DCU0_B4 0x1902
  192. VF610_PAD_PTE26__DCU0_B5 0x1902
  193. VF610_PAD_PTE27__DCU0_B6 0x1902
  194. VF610_PAD_PTE28__DCU0_B7 0x1902
  195. >;
  196. };
  197. pinctrl_dspi1: dspi1grp {
  198. fsl,pins = <
  199. VF610_PAD_PTD5__DSPI1_CS0 0x33e2
  200. VF610_PAD_PTD6__DSPI1_SIN 0x33e1
  201. VF610_PAD_PTD7__DSPI1_SOUT 0x33e2
  202. VF610_PAD_PTD8__DSPI1_SCK 0x33e2
  203. >;
  204. };
  205. pinctrl_esdhc1: esdhc1grp {
  206. fsl,pins = <
  207. VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
  208. VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
  209. VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
  210. VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
  211. VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
  212. VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
  213. VF610_PAD_PTB20__GPIO_42 0x219d
  214. >;
  215. };
  216. pinctrl_fec1: fec1grp {
  217. fsl,pins = <
  218. VF610_PAD_PTA6__RMII_CLKOUT 0x30d2
  219. VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
  220. VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
  221. VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
  222. VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
  223. VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
  224. VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
  225. VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
  226. VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
  227. VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
  228. >;
  229. };
  230. pinctrl_gpio_bl_on: gpio_bl_on {
  231. fsl,pins = <
  232. VF610_PAD_PTC0__GPIO_45 0x22ef
  233. >;
  234. };
  235. pinctrl_i2c0: i2c0grp {
  236. fsl,pins = <
  237. VF610_PAD_PTB14__I2C0_SCL 0x37ff
  238. VF610_PAD_PTB15__I2C0_SDA 0x37ff
  239. >;
  240. };
  241. pinctrl_i2c0_gpio: i2c0gpiogrp {
  242. fsl,pins = <
  243. VF610_PAD_PTB14__GPIO_36 0x37ff
  244. VF610_PAD_PTB15__GPIO_37 0x37ff
  245. >;
  246. };
  247. pinctrl_nfc: nfcgrp {
  248. fsl,pins = <
  249. VF610_PAD_PTD23__NF_IO7 0x28df
  250. VF610_PAD_PTD22__NF_IO6 0x28df
  251. VF610_PAD_PTD21__NF_IO5 0x28df
  252. VF610_PAD_PTD20__NF_IO4 0x28df
  253. VF610_PAD_PTD19__NF_IO3 0x28df
  254. VF610_PAD_PTD18__NF_IO2 0x28df
  255. VF610_PAD_PTD17__NF_IO1 0x28df
  256. VF610_PAD_PTD16__NF_IO0 0x28df
  257. VF610_PAD_PTB24__NF_WE_B 0x28c2
  258. VF610_PAD_PTB25__NF_CE0_B 0x28c2
  259. VF610_PAD_PTB27__NF_RE_B 0x28c2
  260. VF610_PAD_PTC26__NF_RB_B 0x283d
  261. VF610_PAD_PTC27__NF_ALE 0x28c2
  262. VF610_PAD_PTC28__NF_CLE 0x28c2
  263. >;
  264. };
  265. pinctrl_pwm0: pwm0grp {
  266. fsl,pins = <
  267. VF610_PAD_PTB0__FTM0_CH0 0x1182
  268. VF610_PAD_PTB1__FTM0_CH1 0x1182
  269. >;
  270. };
  271. pinctrl_pwm1: pwm1grp {
  272. fsl,pins = <
  273. VF610_PAD_PTB8__FTM1_CH0 0x1182
  274. VF610_PAD_PTB9__FTM1_CH1 0x1182
  275. >;
  276. };
  277. pinctrl_uart0: uart0grp {
  278. fsl,pins = <
  279. VF610_PAD_PTB10__UART0_TX 0x21a2
  280. VF610_PAD_PTB11__UART0_RX 0x21a1
  281. VF610_PAD_PTB12__UART0_RTS 0x21a2
  282. VF610_PAD_PTB13__UART0_CTS 0x21a1
  283. >;
  284. };
  285. pinctrl_uart1: uart1grp {
  286. fsl,pins = <
  287. VF610_PAD_PTB4__UART1_TX 0x21a2
  288. VF610_PAD_PTB5__UART1_RX 0x21a1
  289. >;
  290. };
  291. pinctrl_uart2: uart2grp {
  292. fsl,pins = <
  293. VF610_PAD_PTD0__UART2_TX 0x21a2
  294. VF610_PAD_PTD1__UART2_RX 0x21a1
  295. VF610_PAD_PTD2__UART2_RTS 0x21a2
  296. VF610_PAD_PTD3__UART2_CTS 0x21a1
  297. >;
  298. };
  299. pinctrl_usbh1_reg: gpio_usb_vbus {
  300. fsl,pins = <
  301. VF610_PAD_PTD4__GPIO_83 0x22ed
  302. >;
  303. };
  304. };
  305. };