tegra20-ventana.dts 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/thermal/thermal.h>
  5. #include "tegra20.dtsi"
  6. #include "tegra20-cpu-opp.dtsi"
  7. #include "tegra20-cpu-opp-microvolt.dtsi"
  8. / {
  9. model = "NVIDIA Tegra20 Ventana evaluation board";
  10. compatible = "nvidia,ventana", "nvidia,tegra20";
  11. aliases {
  12. rtc0 = "/i2c@7000d000/tps6586x@34";
  13. rtc1 = "/rtc@7000e000";
  14. serial0 = &uartd;
  15. };
  16. chosen {
  17. stdout-path = "serial0:115200n8";
  18. };
  19. memory@0 {
  20. reg = <0x00000000 0x40000000>;
  21. };
  22. host1x@50000000 {
  23. dc@54200000 {
  24. rgb {
  25. status = "okay";
  26. nvidia,panel = <&panel>;
  27. };
  28. };
  29. hdmi@54280000 {
  30. status = "okay";
  31. vdd-supply = <&hdmi_vdd_reg>;
  32. pll-supply = <&hdmi_pll_reg>;
  33. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  34. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  35. GPIO_ACTIVE_HIGH>;
  36. };
  37. };
  38. pinmux@70000014 {
  39. pinctrl-names = "default";
  40. pinctrl-0 = <&state_default>;
  41. state_default: pinmux {
  42. ata {
  43. nvidia,pins = "ata";
  44. nvidia,function = "ide";
  45. };
  46. atb {
  47. nvidia,pins = "atb", "gma", "gme";
  48. nvidia,function = "sdio4";
  49. };
  50. atc {
  51. nvidia,pins = "atc";
  52. nvidia,function = "nand";
  53. };
  54. atd {
  55. nvidia,pins = "atd", "ate", "gmb", "spia",
  56. "spib", "spic";
  57. nvidia,function = "gmi";
  58. };
  59. cdev1 {
  60. nvidia,pins = "cdev1";
  61. nvidia,function = "plla_out";
  62. };
  63. cdev2 {
  64. nvidia,pins = "cdev2";
  65. nvidia,function = "pllp_out4";
  66. };
  67. crtp {
  68. nvidia,pins = "crtp", "lm1";
  69. nvidia,function = "crt";
  70. };
  71. csus {
  72. nvidia,pins = "csus";
  73. nvidia,function = "vi_sensor_clk";
  74. };
  75. dap1 {
  76. nvidia,pins = "dap1";
  77. nvidia,function = "dap1";
  78. };
  79. dap2 {
  80. nvidia,pins = "dap2";
  81. nvidia,function = "dap2";
  82. };
  83. dap3 {
  84. nvidia,pins = "dap3";
  85. nvidia,function = "dap3";
  86. };
  87. dap4 {
  88. nvidia,pins = "dap4";
  89. nvidia,function = "dap4";
  90. };
  91. dta {
  92. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  93. nvidia,function = "vi";
  94. };
  95. dtf {
  96. nvidia,pins = "dtf";
  97. nvidia,function = "i2c3";
  98. };
  99. gmc {
  100. nvidia,pins = "gmc";
  101. nvidia,function = "uartd";
  102. };
  103. gmd {
  104. nvidia,pins = "gmd";
  105. nvidia,function = "sflash";
  106. };
  107. gpu {
  108. nvidia,pins = "gpu";
  109. nvidia,function = "pwm";
  110. };
  111. gpu7 {
  112. nvidia,pins = "gpu7";
  113. nvidia,function = "rtck";
  114. };
  115. gpv {
  116. nvidia,pins = "gpv", "slxa", "slxk";
  117. nvidia,function = "pcie";
  118. };
  119. hdint {
  120. nvidia,pins = "hdint";
  121. nvidia,function = "hdmi";
  122. };
  123. i2cp {
  124. nvidia,pins = "i2cp";
  125. nvidia,function = "i2cp";
  126. };
  127. irrx {
  128. nvidia,pins = "irrx", "irtx";
  129. nvidia,function = "uartb";
  130. };
  131. kbca {
  132. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  133. "kbce", "kbcf";
  134. nvidia,function = "kbc";
  135. };
  136. lcsn {
  137. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  138. "lsdi", "lvp0";
  139. nvidia,function = "rsvd4";
  140. };
  141. ld0 {
  142. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  143. "ld5", "ld6", "ld7", "ld8", "ld9",
  144. "ld10", "ld11", "ld12", "ld13", "ld14",
  145. "ld15", "ld16", "ld17", "ldi", "lhp0",
  146. "lhp1", "lhp2", "lhs", "lpp", "lpw0",
  147. "lpw2", "lsc0", "lsc1", "lsck", "lsda",
  148. "lspi", "lvp1", "lvs";
  149. nvidia,function = "displaya";
  150. };
  151. owc {
  152. nvidia,pins = "owc", "spdi", "spdo", "uac";
  153. nvidia,function = "rsvd2";
  154. };
  155. pmc {
  156. nvidia,pins = "pmc";
  157. nvidia,function = "pwr_on";
  158. };
  159. rm {
  160. nvidia,pins = "rm";
  161. nvidia,function = "i2c1";
  162. };
  163. sdb {
  164. nvidia,pins = "sdb", "sdc", "sdd", "slxc";
  165. nvidia,function = "sdio3";
  166. };
  167. sdio1 {
  168. nvidia,pins = "sdio1";
  169. nvidia,function = "sdio1";
  170. };
  171. slxd {
  172. nvidia,pins = "slxd";
  173. nvidia,function = "spdif";
  174. };
  175. spid {
  176. nvidia,pins = "spid", "spie", "spif";
  177. nvidia,function = "spi1";
  178. };
  179. spig {
  180. nvidia,pins = "spig", "spih";
  181. nvidia,function = "spi2_alt";
  182. };
  183. uaa {
  184. nvidia,pins = "uaa", "uab", "uda";
  185. nvidia,function = "ulpi";
  186. };
  187. uad {
  188. nvidia,pins = "uad";
  189. nvidia,function = "irda";
  190. };
  191. uca {
  192. nvidia,pins = "uca", "ucb";
  193. nvidia,function = "uartc";
  194. };
  195. conf_ata {
  196. nvidia,pins = "ata", "atb", "atc", "atd",
  197. "cdev1", "cdev2", "dap1", "dap2",
  198. "dap4", "ddc", "dtf", "gma", "gmc",
  199. "gme", "gpu", "gpu7", "i2cp", "irrx",
  200. "irtx", "pta", "rm", "sdc", "sdd",
  201. "slxc", "slxd", "slxk", "spdi", "spdo",
  202. "uac", "uad", "uca", "ucb", "uda";
  203. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  204. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  205. };
  206. conf_ate {
  207. nvidia,pins = "ate", "csus", "dap3", "gmd",
  208. "gpv", "owc", "spia", "spib", "spic",
  209. "spid", "spie", "spig";
  210. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  211. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  212. };
  213. conf_ck32 {
  214. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  215. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  216. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  217. };
  218. conf_crtp {
  219. nvidia,pins = "crtp", "gmb", "slxa", "spih";
  220. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  221. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  222. };
  223. conf_dta {
  224. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  225. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  226. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  227. };
  228. conf_dte {
  229. nvidia,pins = "dte", "spif";
  230. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  231. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  232. };
  233. conf_hdint {
  234. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  235. "lpw1", "lsck", "lsda", "lsdi", "lvp0";
  236. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  237. };
  238. conf_kbca {
  239. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  240. "kbce", "kbcf", "sdio1", "uaa", "uab";
  241. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  242. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  243. };
  244. conf_lc {
  245. nvidia,pins = "lc", "ls";
  246. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  247. };
  248. conf_ld0 {
  249. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  250. "ld5", "ld6", "ld7", "ld8", "ld9",
  251. "ld10", "ld11", "ld12", "ld13", "ld14",
  252. "ld15", "ld16", "ld17", "ldi", "lhp0",
  253. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  254. "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
  255. "lvp1", "lvs", "pmc", "sdb";
  256. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  257. };
  258. conf_ld17_0 {
  259. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  260. "ld23_22";
  261. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  262. };
  263. drive_sdio1 {
  264. nvidia,pins = "drive_sdio1";
  265. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  266. nvidia,schmitt = <TEGRA_PIN_ENABLE>;
  267. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
  268. nvidia,pull-down-strength = <31>;
  269. nvidia,pull-up-strength = <31>;
  270. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  271. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  272. };
  273. };
  274. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  275. ddc {
  276. nvidia,pins = "ddc";
  277. nvidia,function = "i2c2";
  278. };
  279. pta {
  280. nvidia,pins = "pta";
  281. nvidia,function = "rsvd4";
  282. };
  283. };
  284. state_i2cmux_pta: pinmux_i2cmux_pta {
  285. ddc {
  286. nvidia,pins = "ddc";
  287. nvidia,function = "rsvd4";
  288. };
  289. pta {
  290. nvidia,pins = "pta";
  291. nvidia,function = "i2c2";
  292. };
  293. };
  294. state_i2cmux_idle: pinmux_i2cmux_idle {
  295. ddc {
  296. nvidia,pins = "ddc";
  297. nvidia,function = "rsvd4";
  298. };
  299. pta {
  300. nvidia,pins = "pta";
  301. nvidia,function = "rsvd4";
  302. };
  303. };
  304. };
  305. i2s@70002800 {
  306. status = "okay";
  307. };
  308. serial@70006300 {
  309. status = "okay";
  310. };
  311. pwm: pwm@7000a000 {
  312. status = "okay";
  313. };
  314. i2c@7000c000 {
  315. status = "okay";
  316. clock-frequency = <400000>;
  317. wm8903: wm8903@1a {
  318. compatible = "wlf,wm8903";
  319. reg = <0x1a>;
  320. interrupt-parent = <&gpio>;
  321. interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
  322. gpio-controller;
  323. #gpio-cells = <2>;
  324. micdet-cfg = <0>;
  325. micdet-delay = <100>;
  326. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  327. };
  328. /* ALS and proximity sensor */
  329. isl29018@44 {
  330. compatible = "isil,isl29018";
  331. reg = <0x44>;
  332. interrupt-parent = <&gpio>;
  333. interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
  334. };
  335. };
  336. i2c@7000c400 {
  337. status = "okay";
  338. clock-frequency = <100000>;
  339. };
  340. i2cmux {
  341. compatible = "i2c-mux-pinctrl";
  342. #address-cells = <1>;
  343. #size-cells = <0>;
  344. i2c-parent = <&{/i2c@7000c400}>;
  345. pinctrl-names = "ddc", "pta", "idle";
  346. pinctrl-0 = <&state_i2cmux_ddc>;
  347. pinctrl-1 = <&state_i2cmux_pta>;
  348. pinctrl-2 = <&state_i2cmux_idle>;
  349. hdmi_ddc: i2c@0 {
  350. reg = <0>;
  351. #address-cells = <1>;
  352. #size-cells = <0>;
  353. };
  354. lvds_ddc: i2c@1 {
  355. reg = <1>;
  356. #address-cells = <1>;
  357. #size-cells = <0>;
  358. };
  359. };
  360. i2c@7000c500 {
  361. status = "okay";
  362. clock-frequency = <400000>;
  363. };
  364. i2c@7000d000 {
  365. status = "okay";
  366. clock-frequency = <400000>;
  367. pmic: tps6586x@34 {
  368. compatible = "ti,tps6586x";
  369. reg = <0x34>;
  370. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  371. ti,system-power-controller;
  372. #gpio-cells = <2>;
  373. gpio-controller;
  374. sys-supply = <&vdd_5v0_reg>;
  375. vin-sm0-supply = <&sys_reg>;
  376. vin-sm1-supply = <&sys_reg>;
  377. vin-sm2-supply = <&sys_reg>;
  378. vinldo01-supply = <&sm2_reg>;
  379. vinldo23-supply = <&sm2_reg>;
  380. vinldo4-supply = <&sm2_reg>;
  381. vinldo678-supply = <&sm2_reg>;
  382. vinldo9-supply = <&sm2_reg>;
  383. regulators {
  384. sys_reg: sys {
  385. regulator-name = "vdd_sys";
  386. regulator-always-on;
  387. };
  388. vdd_core: sm0 {
  389. regulator-name = "vdd_sm0,vdd_core";
  390. regulator-min-microvolt = <950000>;
  391. regulator-max-microvolt = <1300000>;
  392. regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
  393. regulator-coupled-max-spread = <170000 550000>;
  394. regulator-always-on;
  395. regulator-boot-on;
  396. nvidia,tegra-core-regulator;
  397. };
  398. vdd_cpu: sm1 {
  399. regulator-name = "vdd_sm1,vdd_cpu";
  400. regulator-min-microvolt = <750000>;
  401. regulator-max-microvolt = <1125000>;
  402. regulator-coupled-with = <&vdd_core &rtc_vdd>;
  403. regulator-coupled-max-spread = <550000 550000>;
  404. regulator-always-on;
  405. regulator-boot-on;
  406. nvidia,tegra-cpu-regulator;
  407. };
  408. sm2_reg: sm2 {
  409. regulator-name = "vdd_sm2,vin_ldo*";
  410. regulator-min-microvolt = <3700000>;
  411. regulator-max-microvolt = <3700000>;
  412. regulator-always-on;
  413. };
  414. /* LDO0 is not connected to anything */
  415. ldo1 {
  416. regulator-name = "vdd_ldo1,avdd_pll*";
  417. regulator-min-microvolt = <1100000>;
  418. regulator-max-microvolt = <1100000>;
  419. regulator-always-on;
  420. };
  421. rtc_vdd: ldo2 {
  422. regulator-name = "vdd_ldo2,vdd_rtc";
  423. regulator-min-microvolt = <950000>;
  424. regulator-max-microvolt = <1300000>;
  425. regulator-coupled-with = <&vdd_core &vdd_cpu>;
  426. regulator-coupled-max-spread = <170000 550000>;
  427. regulator-always-on;
  428. regulator-boot-on;
  429. nvidia,tegra-rtc-regulator;
  430. };
  431. ldo3 {
  432. regulator-name = "vdd_ldo3,avdd_usb*";
  433. regulator-min-microvolt = <3300000>;
  434. regulator-max-microvolt = <3300000>;
  435. regulator-always-on;
  436. };
  437. ldo4 {
  438. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  439. regulator-min-microvolt = <1800000>;
  440. regulator-max-microvolt = <1800000>;
  441. regulator-always-on;
  442. };
  443. ldo5 {
  444. regulator-name = "vdd_ldo5,vcore_mmc";
  445. regulator-min-microvolt = <2850000>;
  446. regulator-max-microvolt = <2850000>;
  447. regulator-always-on;
  448. };
  449. ldo6 {
  450. regulator-name = "vdd_ldo6,avdd_vdac";
  451. regulator-min-microvolt = <1800000>;
  452. regulator-max-microvolt = <1800000>;
  453. };
  454. hdmi_vdd_reg: ldo7 {
  455. regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
  456. regulator-min-microvolt = <3300000>;
  457. regulator-max-microvolt = <3300000>;
  458. };
  459. hdmi_pll_reg: ldo8 {
  460. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  461. regulator-min-microvolt = <1800000>;
  462. regulator-max-microvolt = <1800000>;
  463. };
  464. ldo9 {
  465. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  466. regulator-min-microvolt = <2850000>;
  467. regulator-max-microvolt = <2850000>;
  468. regulator-always-on;
  469. };
  470. ldo_rtc {
  471. regulator-name = "vdd_rtc_out,vdd_cell";
  472. regulator-min-microvolt = <3300000>;
  473. regulator-max-microvolt = <3300000>;
  474. regulator-always-on;
  475. };
  476. };
  477. };
  478. nct1008: temperature-sensor@4c {
  479. compatible = "onnn,nct1008";
  480. reg = <0x4c>;
  481. #thermal-sensor-cells = <1>;
  482. };
  483. };
  484. pmc@7000e400 {
  485. nvidia,invert-interrupt;
  486. nvidia,suspend-mode = <1>;
  487. nvidia,cpu-pwr-good-time = <2000>;
  488. nvidia,cpu-pwr-off-time = <100>;
  489. nvidia,core-pwr-good-time = <3845 3845>;
  490. nvidia,core-pwr-off-time = <458>;
  491. nvidia,sys-clock-req-active-high;
  492. core-supply = <&vdd_core>;
  493. };
  494. usb@c5000000 {
  495. status = "okay";
  496. };
  497. usb-phy@c5000000 {
  498. status = "okay";
  499. };
  500. usb@c5004000 {
  501. status = "okay";
  502. };
  503. usb-phy@c5004000 {
  504. status = "okay";
  505. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  506. GPIO_ACTIVE_LOW>;
  507. };
  508. usb@c5008000 {
  509. status = "okay";
  510. };
  511. usb-phy@c5008000 {
  512. status = "okay";
  513. };
  514. mmc@c8000000 {
  515. status = "okay";
  516. power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  517. bus-width = <4>;
  518. keep-power-in-suspend;
  519. };
  520. mmc@c8000400 {
  521. status = "okay";
  522. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  523. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  524. power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  525. bus-width = <4>;
  526. };
  527. mmc@c8000600 {
  528. status = "okay";
  529. bus-width = <8>;
  530. non-removable;
  531. };
  532. backlight: backlight {
  533. compatible = "pwm-backlight";
  534. enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
  535. power-supply = <&vdd_bl_reg>;
  536. pwms = <&pwm 2 5000000>;
  537. brightness-levels = <0 4 8 16 32 64 128 255>;
  538. default-brightness-level = <6>;
  539. };
  540. clk32k_in: clock-32k {
  541. compatible = "fixed-clock";
  542. clock-frequency = <32768>;
  543. #clock-cells = <0>;
  544. };
  545. cpus {
  546. cpu0: cpu@0 {
  547. cpu-supply = <&vdd_cpu>;
  548. operating-points-v2 = <&cpu0_opp_table>;
  549. #cooling-cells = <2>;
  550. };
  551. cpu1: cpu@1 {
  552. cpu-supply = <&vdd_cpu>;
  553. operating-points-v2 = <&cpu0_opp_table>;
  554. #cooling-cells = <2>;
  555. };
  556. };
  557. gpio-keys {
  558. compatible = "gpio-keys";
  559. key-power {
  560. label = "Power";
  561. gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  562. linux,code = <KEY_POWER>;
  563. wakeup-source;
  564. };
  565. };
  566. panel: panel {
  567. compatible = "chunghwa,claa101wa01a";
  568. power-supply = <&vdd_pnl_reg>;
  569. enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
  570. backlight = <&backlight>;
  571. ddc-i2c-bus = <&lvds_ddc>;
  572. };
  573. vdd_5v0_reg: regulator-5v0 {
  574. compatible = "regulator-fixed";
  575. regulator-name = "vdd_5v0";
  576. regulator-min-microvolt = <5000000>;
  577. regulator-max-microvolt = <5000000>;
  578. regulator-always-on;
  579. };
  580. regulator-1v5 {
  581. compatible = "regulator-fixed";
  582. regulator-name = "vdd_1v5";
  583. regulator-min-microvolt = <1500000>;
  584. regulator-max-microvolt = <1500000>;
  585. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  586. };
  587. regulator-1v2 {
  588. compatible = "regulator-fixed";
  589. regulator-name = "vdd_1v2";
  590. regulator-min-microvolt = <1200000>;
  591. regulator-max-microvolt = <1200000>;
  592. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  593. enable-active-high;
  594. };
  595. vdd_pnl_reg: regulator-pnl {
  596. compatible = "regulator-fixed";
  597. regulator-name = "vdd_pnl";
  598. regulator-min-microvolt = <2800000>;
  599. regulator-max-microvolt = <2800000>;
  600. gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
  601. enable-active-high;
  602. };
  603. vdd_bl_reg: regulator-bl {
  604. compatible = "regulator-fixed";
  605. regulator-name = "vdd_bl";
  606. regulator-min-microvolt = <2800000>;
  607. regulator-max-microvolt = <2800000>;
  608. gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
  609. enable-active-high;
  610. };
  611. sound {
  612. compatible = "nvidia,tegra-audio-wm8903-ventana",
  613. "nvidia,tegra-audio-wm8903";
  614. nvidia,model = "NVIDIA Tegra Ventana";
  615. nvidia,audio-routing =
  616. "Headphone Jack", "HPOUTR",
  617. "Headphone Jack", "HPOUTL",
  618. "Int Spk", "ROP",
  619. "Int Spk", "RON",
  620. "Int Spk", "LOP",
  621. "Int Spk", "LON",
  622. "Mic Jack", "MICBIAS",
  623. "IN1L", "Mic Jack";
  624. nvidia,i2s-controller = <&tegra_i2s1>;
  625. nvidia,audio-codec = <&wm8903>;
  626. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  627. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
  628. nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
  629. GPIO_ACTIVE_HIGH>;
  630. nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
  631. GPIO_ACTIVE_HIGH>;
  632. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  633. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  634. <&tegra_car TEGRA20_CLK_CDEV1>;
  635. clock-names = "pll_a", "pll_a_out0", "mclk";
  636. };
  637. thermal-zones {
  638. cpu-thermal {
  639. polling-delay-passive = <1000>; /* milliseconds */
  640. polling-delay = <5000>; /* milliseconds */
  641. thermal-sensors = <&nct1008 1>;
  642. trips {
  643. trip0: cpu-alert0 {
  644. /* start throttling at 50C */
  645. temperature = <50000>;
  646. hysteresis = <200>;
  647. type = "passive";
  648. };
  649. trip1: cpu-crit {
  650. /* shut down at 60C */
  651. temperature = <60000>;
  652. hysteresis = <2000>;
  653. type = "critical";
  654. };
  655. };
  656. cooling-maps {
  657. map0 {
  658. trip = <&trip0>;
  659. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  660. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  661. };
  662. };
  663. };
  664. };
  665. };